Motorola TMS320C6711D User Manual
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
1
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
D
Excellent-Price/Performance Floating-Point
Digital Signal Processor (DSP):
TMS320C6711D
− Eight 32-Bit Instructions/Cycle
− 167-, 200-, 250-MHz Clock Rates
− 6-, 5-, 4-ns Instruction Cycle Time
− 1000, 1200, 1500 MFLOPS
Digital Signal Processor (DSP):
TMS320C6711D
− Eight 32-Bit Instructions/Cycle
− 167-, 200-, 250-MHz Clock Rates
− 6-, 5-, 4-ns Instruction Cycle Time
− 1000, 1200, 1500 MFLOPS
D
Advanced Very Long Instruction Word
(VLIW) C67x
(VLIW) C67x
DSP Core
− Eight Highly Independent Functional
Units:
− Four ALUs (Floating- and Fixed-Point)
− Two ALUs (Fixed-Point)
− Two Multipliers (Floating- and
− Four ALUs (Floating- and Fixed-Point)
− Two ALUs (Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
− All Instructions Conditional
D
Instruction Set Features
− Hardware Support for IEEE
− Hardware Support for IEEE
Single-Precision and Double-Precision
Instructions
Instructions
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
D
L1/L2 Memory Architecture
− 32K-Bit (4K-Byte) L1P Program Cache
− 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
− 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
(Flexible Data/Program Allocation)
D
Device Configuration
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian
D
Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
Controller (16 Independent Channels)
D
32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
− 256M-Byte Total Addressable External
Memory Space
D
16-Bit Host-Port Interface (HPI)
D
Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola
)
D
Two 32-Bit General-Purpose Timers
D
Flexible Software Configurable PLL-Based
Clock Generator Module
Clock Generator Module
D
A Dedicated General-Purpose Input/Output
(GPIO) Module With 5 Pins
(GPIO) Module With 5 Pins
D
IEEE-1149.1 (JTAG
†
)
Boundary-Scan-Compatible
D
272-Pin Ball Grid Array (BGA) Package
(GDP and ZDP Suffixes)
(GDP and ZDP Suffixes)
D
CMOS Technology
− 0.13-
− 0.13-
µ
m/6-Level Copper Metal Process
D
3.3-V I/O, 1.4-V Internal (−250)
D
3.3-V I/O, 1.20-V Internal
‡
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2005, Texas Instruments Incorporated
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TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
‡ These values are compatible with existing 1.26V designs.