Motorola SC140 User Manual
A-2
Using the SC140 Enhanced OnCE Stopwatch Timer
Code A-2. EOnCE_registers.h
/* EOnCE registers */
#define EXCP_TABLE 0x7000
#define REG_BASE_ADDRESS 0x00effe00 /* EOnCE Status register */
#define EXCP_TABLE 0x7000
#define REG_BASE_ADDRESS 0x00effe00 /* EOnCE Status register */
#ifdef COMPILER_BETA_1_BUG
long EE_CTRL = REG_BASE_ADDRESS+0x18; /* EOnCE EE pins Control register */
long EDCA1_CTRL = REG_BASE_ADDRESS+0x44; /* EOnCE EDCA #1 Control register */
long EDCA1_REFA = REG_BASE_ADDRESS+0x64; /* EOnCE EDCA #1 Reference Value A */
long EDCA1_REFB = REG_BASE_ADDRESS+0x84; /* EOnCE EDCA #1 Reference Value B */
long EDCA1_MASK = REG_BASE_ADDRESS+0xc4; /* EOnCE EDCA #1 Mask Register */
long ECNT_CTRL = REG_BASE_ADDRESS+0x100; /* EOnCE Counter Control register */
long ECNT_VAL = REG_BASE_ADDRESS+0x104; /* EOnCE Counter Value register */
long ECNT_EXT = REG_BASE_ADDRESS+0x108; /* EOnCE Extension Counter Value */
#else
#define EMCR REG_BASE_ADDRESS+0x4 /* EOnCE Monitor and Control register */
#define ERCV REG_BASE_ADDRESS+0x8 /* EOnCE Receive register */
#define ETRSMT0 REG_BASE_ADDRESS+0x10 /* EOnCE Receive register */
#define ETRSMT1 REG_BASE_ADDRESS+0x14 /* EOnCE Receive register */
#define EE_CTRL REG_BASE_ADDRESS+0x18 /* EOnCE EE pins Control register */
#define PC_EX REG_BASE_ADDRESS+0x1c /* EOnCE Exception PC register */
#define EDCA0_CTRL REG_BASE_ADDRESS+0x40 /* EOnCE EDCA #0 Control register */
#define EDCA1_CTRL REG_BASE_ADDRESS+0x44 /* EOnCE EDCA #1 Control register */
#define EDCA2_CTRL REG_BASE_ADDRESS+0x48 /* EOnCE EDCA #2 Control register */
#define EDCA3_CTRL REG_BASE_ADDRESS+0x4c /* EOnCE EDCA #3 Control register */
#define EDCA4_CTRL REG_BASE_ADDRESS+0x50 /* EOnCE EDCA #4 Control register */
#define EDCA5_CTRL REG_BASE_ADDRESS+0x54 /* EOnCE EDCA #5 Control register */
#define EDCA0_REFA REG_BASE_ADDRESS+0x60 /* EOnCE EDCA #0 Reference Value A */
#define EDCA1_REFA REG_BASE_ADDRESS+0x64 /* EOnCE EDCA #1 Reference Value A */
#define EDCA2_REFA REG_BASE_ADDRESS+0x68 /* EOnCE EDCA #2 Reference Value A */
#define EDCA3_REFA REG_BASE_ADDRESS+0x6c /* EOnCE EDCA #3 Reference Value A */
#define EDCA4_REFA REG_BASE_ADDRESS+0x70 /* EOnCE EDCA #4 Reference Value A */
#define EDCA5_REFA REG_BASE_ADDRESS+0x74 /* EOnCE EDCA #5 Reference Value A */
#define EDCA0_REFB REG_BASE_ADDRESS+0x80 /* EOnCE EDCA #0 Reference Value B */
#define EDCA1_REFB REG_BASE_ADDRESS+0x84 /* EOnCE EDCA #1 Reference Value B */
#define EDCA2_REFB REG_BASE_ADDRESS+0x88 /* EOnCE EDCA #2 Reference Value B */
#define EDCA3_REFB REG_BASE_ADDRESS+0x8c /* EOnCE EDCA #3 Reference Value B */
#define EDCA4_REFB REG_BASE_ADDRESS+0x90 /* EOnCE EDCA #4 Reference Value B */
#define EDCA5_REFB REG_BASE_ADDRESS+0x94 /* EOnCE EDCA #5 Reference Value B */
#define EDCA0_MASK REG_BASE_ADDRESS+0xc0 /* EOnCE EDCA #0 Mask Register */
#define EDCA1_MASK REG_BASE_ADDRESS+0xc4 /* EOnCE EDCA #1 Mask Register */
#define EDCA2_MASK REG_BASE_ADDRESS+0xc8 /* EOnCE EDCA #2 Mask Register */
#define EDCA3_MASK REG_BASE_ADDRESS+0xcc /* EOnCE EDCA #3 Mask Register */
#define EDCA4_MASK REG_BASE_ADDRESS+0xd0 /* EOnCE EDCA #4 Mask Register */
#define EDCA5_MASK REG_BASE_ADDRESS+0xd4 /* EOnCE EDCA #5 Mask Register */
#define EDCD_CTRL REG_BASE_ADDRESS+0xe0 /* EOnCE EDCD Control register */
#define EDCD_REF REG_BASE_ADDRESS+0xe4 /* EOnCE EDCD Reference Value */
#define EDCD_MASK REG_BASE_ADDRESS+0xe8 /* EOnCE EDCD Mask register */
#define ECNT_CTRL REG_BASE_ADDRESS+0x100 /* EOnCE Counter Control register */
#define ECNT_VAL REG_BASE_ADDRESS+0x104 /* EOnCE Counter Value register */
#define ECNT_EXT REG_BASE_ADDRESS+0x108 /* EOnCE Extension Counter Value */
#define ESEL_CTRL REG_BASE_ADDRESS+0x120 /* EOnCE Selector Control register */
#define ESEL_DM REG_BASE_ADDRESS+0x124 /* EOnCE Selector DM Mask */
#define ESEL_DI REG_BASE_ADDRESS+0x128 /* EOnCE Selector DI Mask */
#define ESEL_RST REG_BASE_ADDRESS+0x12c /* EOnCE Selector RST Mask */
#define ESEL_ETB REG_BASE_ADDRESS+0x130 /* EOnCE Selector ETB Mask */
#define ESEL_DTB REG_BASE_ADDRESS+0x134 /* EOnCE Selector DTB Mask */
#define TB_CTRL REG_BASE_ADDRESS+0x140 /* EOnCE Trace Buffer Control register */
#define TB_RD REG_BASE_ADDRESS+0x144 /* EOnCE Trace Buffer Read Pointer */
#define TB_WR REG_BASE_ADDRESS+0x148 /* EOnCE Trace Buffer Write Pointer */
#define TB_BUFF REG_BASE_ADDRESS+0x14c /* EOnCE Trace Buffer */
#define TRAP_EXCP EXCP_TABLE /* trap instruction exception */
#define ILL_EXCP EXCP_TABLE+0x80 /* illegal set or illegal instruction exception */
#define DBG_EXCP EXCP_TABLE+0xc0 /* debug exception (eonce) */
#define OVFL_EXCP EXCP_TABLE+0x100 /* overflow exception */
#define AUTO_NMI_EXCP EXCP_TABLE+0x180 /* default nmi exception vector */
#define AUTO_EXT_EXCP EXCP_TABLE+0x1c0 /* default external exception */
#define NMI_EXCP EXCP_TABLE+0x280 /* nmi exception vector (arbitrary address) */
#define EXT_EXCP EXCP_TABLE+0x2c0 /* external exception (arbitrary address) */
#endif
long EE_CTRL = REG_BASE_ADDRESS+0x18; /* EOnCE EE pins Control register */
long EDCA1_CTRL = REG_BASE_ADDRESS+0x44; /* EOnCE EDCA #1 Control register */
long EDCA1_REFA = REG_BASE_ADDRESS+0x64; /* EOnCE EDCA #1 Reference Value A */
long EDCA1_REFB = REG_BASE_ADDRESS+0x84; /* EOnCE EDCA #1 Reference Value B */
long EDCA1_MASK = REG_BASE_ADDRESS+0xc4; /* EOnCE EDCA #1 Mask Register */
long ECNT_CTRL = REG_BASE_ADDRESS+0x100; /* EOnCE Counter Control register */
long ECNT_VAL = REG_BASE_ADDRESS+0x104; /* EOnCE Counter Value register */
long ECNT_EXT = REG_BASE_ADDRESS+0x108; /* EOnCE Extension Counter Value */
#else
#define EMCR REG_BASE_ADDRESS+0x4 /* EOnCE Monitor and Control register */
#define ERCV REG_BASE_ADDRESS+0x8 /* EOnCE Receive register */
#define ETRSMT0 REG_BASE_ADDRESS+0x10 /* EOnCE Receive register */
#define ETRSMT1 REG_BASE_ADDRESS+0x14 /* EOnCE Receive register */
#define EE_CTRL REG_BASE_ADDRESS+0x18 /* EOnCE EE pins Control register */
#define PC_EX REG_BASE_ADDRESS+0x1c /* EOnCE Exception PC register */
#define EDCA0_CTRL REG_BASE_ADDRESS+0x40 /* EOnCE EDCA #0 Control register */
#define EDCA1_CTRL REG_BASE_ADDRESS+0x44 /* EOnCE EDCA #1 Control register */
#define EDCA2_CTRL REG_BASE_ADDRESS+0x48 /* EOnCE EDCA #2 Control register */
#define EDCA3_CTRL REG_BASE_ADDRESS+0x4c /* EOnCE EDCA #3 Control register */
#define EDCA4_CTRL REG_BASE_ADDRESS+0x50 /* EOnCE EDCA #4 Control register */
#define EDCA5_CTRL REG_BASE_ADDRESS+0x54 /* EOnCE EDCA #5 Control register */
#define EDCA0_REFA REG_BASE_ADDRESS+0x60 /* EOnCE EDCA #0 Reference Value A */
#define EDCA1_REFA REG_BASE_ADDRESS+0x64 /* EOnCE EDCA #1 Reference Value A */
#define EDCA2_REFA REG_BASE_ADDRESS+0x68 /* EOnCE EDCA #2 Reference Value A */
#define EDCA3_REFA REG_BASE_ADDRESS+0x6c /* EOnCE EDCA #3 Reference Value A */
#define EDCA4_REFA REG_BASE_ADDRESS+0x70 /* EOnCE EDCA #4 Reference Value A */
#define EDCA5_REFA REG_BASE_ADDRESS+0x74 /* EOnCE EDCA #5 Reference Value A */
#define EDCA0_REFB REG_BASE_ADDRESS+0x80 /* EOnCE EDCA #0 Reference Value B */
#define EDCA1_REFB REG_BASE_ADDRESS+0x84 /* EOnCE EDCA #1 Reference Value B */
#define EDCA2_REFB REG_BASE_ADDRESS+0x88 /* EOnCE EDCA #2 Reference Value B */
#define EDCA3_REFB REG_BASE_ADDRESS+0x8c /* EOnCE EDCA #3 Reference Value B */
#define EDCA4_REFB REG_BASE_ADDRESS+0x90 /* EOnCE EDCA #4 Reference Value B */
#define EDCA5_REFB REG_BASE_ADDRESS+0x94 /* EOnCE EDCA #5 Reference Value B */
#define EDCA0_MASK REG_BASE_ADDRESS+0xc0 /* EOnCE EDCA #0 Mask Register */
#define EDCA1_MASK REG_BASE_ADDRESS+0xc4 /* EOnCE EDCA #1 Mask Register */
#define EDCA2_MASK REG_BASE_ADDRESS+0xc8 /* EOnCE EDCA #2 Mask Register */
#define EDCA3_MASK REG_BASE_ADDRESS+0xcc /* EOnCE EDCA #3 Mask Register */
#define EDCA4_MASK REG_BASE_ADDRESS+0xd0 /* EOnCE EDCA #4 Mask Register */
#define EDCA5_MASK REG_BASE_ADDRESS+0xd4 /* EOnCE EDCA #5 Mask Register */
#define EDCD_CTRL REG_BASE_ADDRESS+0xe0 /* EOnCE EDCD Control register */
#define EDCD_REF REG_BASE_ADDRESS+0xe4 /* EOnCE EDCD Reference Value */
#define EDCD_MASK REG_BASE_ADDRESS+0xe8 /* EOnCE EDCD Mask register */
#define ECNT_CTRL REG_BASE_ADDRESS+0x100 /* EOnCE Counter Control register */
#define ECNT_VAL REG_BASE_ADDRESS+0x104 /* EOnCE Counter Value register */
#define ECNT_EXT REG_BASE_ADDRESS+0x108 /* EOnCE Extension Counter Value */
#define ESEL_CTRL REG_BASE_ADDRESS+0x120 /* EOnCE Selector Control register */
#define ESEL_DM REG_BASE_ADDRESS+0x124 /* EOnCE Selector DM Mask */
#define ESEL_DI REG_BASE_ADDRESS+0x128 /* EOnCE Selector DI Mask */
#define ESEL_RST REG_BASE_ADDRESS+0x12c /* EOnCE Selector RST Mask */
#define ESEL_ETB REG_BASE_ADDRESS+0x130 /* EOnCE Selector ETB Mask */
#define ESEL_DTB REG_BASE_ADDRESS+0x134 /* EOnCE Selector DTB Mask */
#define TB_CTRL REG_BASE_ADDRESS+0x140 /* EOnCE Trace Buffer Control register */
#define TB_RD REG_BASE_ADDRESS+0x144 /* EOnCE Trace Buffer Read Pointer */
#define TB_WR REG_BASE_ADDRESS+0x148 /* EOnCE Trace Buffer Write Pointer */
#define TB_BUFF REG_BASE_ADDRESS+0x14c /* EOnCE Trace Buffer */
#define TRAP_EXCP EXCP_TABLE /* trap instruction exception */
#define ILL_EXCP EXCP_TABLE+0x80 /* illegal set or illegal instruction exception */
#define DBG_EXCP EXCP_TABLE+0xc0 /* debug exception (eonce) */
#define OVFL_EXCP EXCP_TABLE+0x100 /* overflow exception */
#define AUTO_NMI_EXCP EXCP_TABLE+0x180 /* default nmi exception vector */
#define AUTO_EXT_EXCP EXCP_TABLE+0x1c0 /* default external exception */
#define NMI_EXCP EXCP_TABLE+0x280 /* nmi exception vector (arbitrary address) */
#define EXT_EXCP EXCP_TABLE+0x2c0 /* external exception (arbitrary address) */
#endif