Cypress CY7C64013C User Manual

Document #: 38-08001 Rev. *B

Page 18 of 51

The USB transmitter is disabled by a Watchdog Reset because the USB Device Address Register is cleared (see Section 18.1).

Otherwise, the USB Controller would respond to all address 0 transactions.
It is possible for the WDR bit of the Processor Status and Control Register (0xFF) to be set following a POR event. The WDR bit

should be ignored If the firmware interrogates the Processor Status and Control Register for a Set condition on the WDR bit and

if the POR (bit 3 of register 0xFF) bit is set.

The CY7C64x13C can be placed into a low-power state by setting the Suspend bit of the Processor Status and Control register.

All logic blocks in the device are turned off except the GPIO interrupt logic and the USB receiver. The clock oscillator and PLL,

as well as the free-running and Watchdog timers, are shut down. Only the occurrence of an enabled GPIO interrupt or non-idle

bus activity at a USB upstream or downstream port wakes the part out of suspend. The Run bit in the Processor Status and

Control Register must be set to resume a part out of suspend.
The clock oscillator restarts immediately after exiting suspend mode. The microcontroller returns to a fully functional state 1 ms

after the oscillator is stable. The microcontroller executes the instruction following the I/O write that placed the device into suspend

mode before servicing any interrupt requests.
The GPIO interrupt allows the controller to wake-up periodically and poll system components while maintaining a very low average

power consumption. To achieve the lowest possible current during suspend mode, all I/O should be held at V

CC

 or Gnd. This also

applies to internal port pins that may not be bonded in a particular package.
Typical code for entering suspend is shown below:

...

; All GPIO set to low-power state (no floating pins)

...

; Enable GPIO interrupts if desired for wake-up

mov a, 09h

; Set suspend and run bits 

iowr FFh

; Write to Status and Control Register - Enter suspend, wait for USB activity (or GPIO Interrupt)

nop

; This executes before any ISR

...

; Remaining code for exiting suspend routine

Last write to 

Watchdog Timer
Register

No write to WDT

register, so WDR
goes HIGH

Execution begins at

Reset Vector 0x0000

t

WATCH

2 ms