Cypress CY7C64013C User Manual
CY7C64013C
CY7C64113C
Document #: 38-08001 Rev. *B
Page 22 of 51
The amount of sink current for the DAC I/O pin is programmable over 16 values based on the contents of the DAC Isink Register
for that output pin. DAC[1:0] are high-current outputs that are programmable from 3.2 mA to 16 mA (typical). DAC[7:2] are low-
current outputs, programmable from 0.2 mA to 1.0 mA (typical).
When the suspend bit in Processor Status and Control Register (see Figure 15-1) is set, the Isink DAC block of the DAC circuitry
When the suspend bit in Processor Status and Control Register (see Figure 15-1) is set, the Isink DAC block of the DAC circuitry
is disabled. Special care should be taken when the CY7C64x13C device is placed in the suspend mode. The DAC Port Data
Register (see Figure 10-2) should normally be loaded with all ‘1’s (0xFF) before setting the suspend bit. If any of the DAC bits
are set to ‘0’ when the device is suspended, that DAC input will float. The floating pin could result in excessive current consumption
by the device, unless an external load places the pin in a deterministic state.
DAC Port Data
ADDRESS 0x30
Bit [1..0]: High Current Output 3.2 mA to 16 mA typical
1= I/O pin is an output pulled HGH through the 14-k
Ω resistor. 0 = I/O pin is an input with an internal 14-kΩ pull-up resistor
Bit [3..2]: Low Current Output 0.2 mA to 1 mA typical
1= I/O pin is an output pulled HGH through the 14-k
Ω resistor. 0 = I/O pin is an input with an internal 14-kΩ pull-up resistor
10.1
DAC Isink Registers
Each DAC I/O pin has an associated DAC Isink register to program the output sink current when the output is driven LOW. The
first Isink register (0x38) controls the current for DAC[0], the second (0x39) for DAC[1], and so on until the Isink register at 0x3F
controls the current to DAC[7].
DAC Sink Register
ADDRESS 0x38 -0x3F
Figure 10-1. Block Diagram of a DAC Pin
Bit #
7
6
5
4
3
2
1
0
Bit Name
DAC[7]
Reserved
Reserved
Reserved
Reserved
DAC[2]
DAC[1]
DAC[0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Figure 10-2. DAC Port Data
Bit #
7
6
5
4
3
2
1
0
Bit Name
Reserved
Reserved
Reserved
Reserved
Isink[3]
Isink[2]
Isink[1]
Isink[0]
Read/Write
W
W
W
W
Reset
-
-
-
-
0
0
0
0
Figure 10-3. DAC Sink Register
V
CC
14 k
Ω
Data
Out
Latch
Internal
Data Bus
DAC Read
DAC Write
Interrupt
Enable
In
te
rrup
t Log
ic
to Interrupt
Controller
Q1
Internal
Buffer
Interrupt
Polarity
Isink
DAC
Isink
Register
4 bits
DAC
I/O Pin
Suspend
(Bit 3 of Register 0xFF)
(Bit 3 of Register 0xFF)