Texas Instruments DM648 DSP User Manual
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4.6
SDRAM Timing 2 Register (SDTIM2)
DDR2 Memory Controller Registers
Like the SDRAM timing 1 register (SDTIM1), the SDRAM timing 2 register (SDTIM2) also configures the
DDR2 memory controller to meet the AC timing specification of the DDR2 memory. See the DDR2
memory data sheet for information on the appropriate values to program each field. The bit fields in the
SDTIM2 register are only writeable when the TIMUNLOCK bit of the SDRAM Configuration register
(SDCFG) is unlocked. SDTIM2 is shown in
DDR2 memory controller to meet the AC timing specification of the DDR2 memory. See the DDR2
memory data sheet for information on the appropriate values to program each field. The bit fields in the
SDTIM2 register are only writeable when the TIMUNLOCK bit of the SDRAM Configuration register
(SDCFG) is unlocked. SDTIM2 is shown in
and described in
Figure 25. SDRAM Timing 2 Register (SDTIM2)
31
25
24
23
22
16
Reserved
T_ODT
T_SXNR
R-0x0
R/W-0x3
R/W-0x7F
15
8
7
5
4
0
T_SXRD
T_RTP
T_CKE
R/W-0xFF
R/W-0x7
R/W-0x1F
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = value is indeterminate after reset;
Table 23. SDRAM Timing 2 Register (SDTIM2) Field Descriptions
Bit
Field
Value
Description
31-25
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
24-23
T_ODT
These bits specify the number of DDR_CLK cycles from ODT enable to write data driven for DDR2
SDRAM. T_ODT must be less than the CAS latency minus one. Calculate using this formula:
SDRAM. T_ODT must be less than the CAS latency minus one. Calculate using this formula:
T_ODT = CAS latency - t
aond
- 1
22-16
T_SXNR
0-7Fh
These bits specify the minimum number of DDR_CLK cycles from a self_refresh exit to any other
command except a read command, minus 1. The value for these bits can be derived from the t
command except a read command, minus 1. The value for these bits can be derived from the t
SXNR
AC timing parameter in the DDR2 data sheet. Calculate using this formula:
T_SXNR = (t
SXNR
/DDR_CLK) - 1
15-8
T_SXRD
0-FFh
These bits specify the minimum number of DDR_CLK cycles from a self_refresh exit to a read
command, minus 1. The value for these bits can be derived from the t
command, minus 1. The value for these bits can be derived from the t
SXRD
AC timing parameter in
the DDR2 data sheet. Calculate using this formula:
T_SXRD = t
SXRD
- 1
7-5
T_RTP
0-7h
These bits specify the minimum number of DDR_CLK cycles from a last read command to a
precharge command, minus 1. The value for these bits can be derived from the t
precharge command, minus 1. The value for these bits can be derived from the t
rtp
AC timing
parameter in the DDR2 data sheet. Calculate using this formula:
T_RTP = (t
rtp
/DDR_CLK) - 1
4-0
T_CKE
0-1Fh
These bits specify the minimum number of DDR_CLK cycles between transitions on the DDR_CKE
pin, minus 1. The value for these bits can be derived from the t
pin, minus 1. The value for these bits can be derived from the t
cke
AC timing parameter in the
DDR2 data sheet. Calculate using this formula:
T_CKE = t
cke
- 1
SPRUEK5A – October 2007
DSP DDR2 Memory Controller
43