Intel BX80635E52697V2 User Manual

Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families

129

Datasheet Volume One of Two

 

Clock multiplying within the processor is provided by the internal phase locked loop 

(PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with 
exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP, 

BCLK{0/1}_DN inputs are provided in 

. These specifications must be met 

while also meeting the associated signal quality specifications outlined in 

An on-die PLL filter solution is implemented on the processor. Refer to 

DC specifications.

Due to the voltage levels supported by other components in the JTAG and Test Access 

Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by 
any other components within the system. Please refer to the Intel® Xeon® Processor 
E5-1600 v2/E5-2600 v2 Product Families – Boundary Scan Description Language 
(BSDL) File 

for more details. A translation buffer should be used to connect to the rest 

of the chain unless one of the other components is capable of accepting an input of the 

appropriate voltage. Two copies of each signal may be required with each driving a 

different voltage level. 

The processor include asynchronous sideband signals that provide asynchronous input, 

output or I/O signals between the processor and the platform or Platform Controller 

Hub. Details can be found in 

 and the applicable platform design guide. 

All Processor Asynchronous Sideband input signals are required to be 

asserted/deasserted for a defined number of BCLKs in order for the processor to 

recognize the proper signal state. Refer to 

 for applicable signal  

integrity specifications.

Processors also include various other signals including power/ground and sense points. 

Details can be found in 

 and the applicable platform design guide.

All V

CC

, V

CCPLL, 

V

SA

, V

CCD, 

V

TTA

, and V

TTD

 lands must be connected to their respective 

processor power planes, while all V

SS

 lands must be connected to the system ground 

plane. For clean on-chip power distribution, processors include lands for all required 

voltage supplies. These are listed in 

.

V

CC

208

Each V

CC

 land must be supplied with the voltage determined by the 

SVID Bus signals. 

 defines the voltage level associated with 

each core SVID pattern.

, and 

 

represent V

CC 

static and transient limits. VCC has a VBOOT setting of 

0.0V.

V

CCPLL

3

Each V

CCPLL

 land is connected to a 1.70 V supply, power the Phase 

Lock Loop (PLL) clock generation circuitry. An on-die PLL filter 

solution is implemented within the processor.