Intel 80960HT User Manual

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32-Bit Parallel Architecture

— Load/Store Architecture

— Sixteen 32-Bit Global Registers

— Sixteen 32-Bit Local Registers

— 1.28 Gbyte Internal Bandwidth 

(80 MHz)

— On-Chip Register Cache

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Processor Core Clock

— 80960HA is 1x Bus Clock

— 80960HD is 2x Bus Clock

— 80960HT is 3x Bus Clock

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Binary Compatible with Other 80960 
Processors

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Issue Up To 150 Million Instructions per 
Second

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High-Performance On-Chip Storage

— 16 Kbyte Four-Way Set-Associative 

Instruction Cache

— 8 Kbyte Four-Way Set-Associative Data 

Cache

— 2 Kbyte General Purpose RAM

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Separate 128-Bit Internal Paths For 
Instructions/Data

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3.3 V Supply Voltage

— 5 V Tolerant Inputs

— TTL Compatible Outputs

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Guarded Memory Unit

— Provides Memory Protection

— User/Supervisor Read/Write/Execute

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32-Bit Demultiplexed Burst Bus

— Per-Byte Parity Generation/Checking

— Address Pipelining Option

— Fully Programmable Wait State Generator

— Supports 8-, 16- or 32-Bit Bus Widths

— 160 Mbyte/s External Bandwidth 

(40 MHz)

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High-Speed Interrupt Controller

— Up to 240 External Interrupts

— 31 Fully Programmable Priorities

— Separate, Non-maskable Interrupt Pin

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Dual On-Chip 32-Bit Timers

— Auto Reload Capability and One-Shot

— CLKIN Prescaling, divided by 1, 2, 4 or 8

— JTAG Support - IEEE 1149.1 Compliant

Order Number: 272495-008

September 2002