Intel 87C196CB User Manual
7-9
CAN SERIAL COMMUNICATIONS CONTROLLER
7.3.4
Error Detection and Management Logic
The CAN controller has several error detection mechanisms, including cyclical redundancy
checking (CRC) and bit coding rules (stuffing and destuffing). The CAN controller generates a
CRC code for transmitted messages and checks the CRC code of incoming messages. The CRC
polynomial has been optimized for control applications with short messages.
checking (CRC) and bit coding rules (stuffing and destuffing). The CAN controller generates a
CRC code for transmitted messages and checks the CRC code of incoming messages. The CRC
polynomial has been optimized for control applications with short messages.
After five consecutive bits of equal value are transmitted, a bit with the opposite polarity is added
to the bit stream. This bit is called a stuff bit; by adding a transition, a stuff bit aids in synchroni-
zation. All message fields are stuffed except the CRC delimiter, the acknowledgment field, and
the end-of-frame field.
to the bit stream. This bit is called a stuff bit; by adding a transition, a stuff bit aids in synchroni-
zation. All message fields are stuffed except the CRC delimiter, the acknowledgment field, and
the end-of-frame field.
Receiving nodes reject data from any message that is corrupted during transmission and send an
error message via the CAN bus. Transmitting nodes monitor the CAN bus for error messages and
automatically repeat a transmission if an error occurs. The following error types are detected:
error message via the CAN bus. Transmitting nodes monitor the CAN bus for error messages and
automatically repeat a transmission if an error occurs. The following error types are detected:
•
stuff error — more than 5 equal bits in a sequence have occurred in a part of a received
message where this is not allowed
message where this is not allowed
•
form error — the fixed-format part of a received frame has the wrong format (for example,
a reserved bit has the wrong value)
a reserved bit has the wrong value)
•
acknowledgment error — this device transmitted a message, but it was not acknowledged
by another node on the CAN bus. (The transmit error counter stops incrementing after 128
acknowledgment errors, so this error type does not cause a bus-off state.)
by another node on the CAN bus. (The transmit error counter stops incrementing after 128
acknowledgment errors, so this error type does not cause a bus-off state.)
•
bit 1 error — the CAN controller tried to send a recessive (logic 1) bit as part of a
transmitted message (with the exception of the arbitration field), but the monitored CAN
bus value was dominant (logic 0)
transmitted message (with the exception of the arbitration field), but the monitored CAN
bus value was dominant (logic 0)
•
bit 0 error — the CAN controller tried to send a dominant (logic 0) bit as part of a
transmitted message (with the exception of the arbitration field), but the monitored CAN
bus value was recessive (logic 1)
transmitted message (with the exception of the arbitration field), but the monitored CAN
bus value was recessive (logic 1)
•
CRC error — the CRC checksum received for an incoming message does not match the
CRC value that the CAN controller calculated for the received data
CRC value that the CAN controller calculated for the received data
The CAN status register indicates the type of the first transmission error that occurred on the
CAN bus and whether an abnormal number of errors have occurred. Two counters (a receive error
counter and a transmit error counter) track the number of errors. The status register’s warning bit
is set when the receive or transmit error counter reaches 96; the bus-off bit is set when either
counter reaches 256. If this occurs, the CAN controller isolates itself from the CAN bus (floats
the TX pin). Software must clear the INIT bit in the control register (Figure 7-6 on page 7-13) to
begin a bus-off recovery sequence.
CAN bus and whether an abnormal number of errors have occurred. Two counters (a receive error
counter and a transmit error counter) track the number of errors. The status register’s warning bit
is set when the receive or transmit error counter reaches 96; the bus-off bit is set when either
counter reaches 256. If this occurs, the CAN controller isolates itself from the CAN bus (floats
the TX pin). Software must clear the INIT bit in the control register (Figure 7-6 on page 7-13) to
begin a bus-off recovery sequence.