Intel 8XC251SP User Manual

5-6

In arithmetic and logical instructions that use indirect addressing, the source operand is always a
byte, and the destination is either the accumulator or a byte register (R0–R15). The source address
is a byte, word, or dword. The two architectures do indirect addressing via different registers:

MCS 251 architecture. Memory is indirectly addressed via word and dword registers:

— Word register (@WRj, j = 0, 2, 4, ..., 30). The 16-bit address in WRj can access

locations 00:0000H–00:FFFFH.

— Dword register (@DRk, k = 0, 4, 8, ..., 28, 56, and 60). The 24 least significant bits can

access the entire 16-Mbyte address space. The upper eight bits of DRk must be 0. If
you use DR60 as a general data pointer, be aware that DR60 is the extended stack
pointer register SPX.

MCS 51 architecture. Instructions use indirect addressing to access on-chip RAM, code
memory, and external data RAM. See the notes in section 5.3.1, “Data Addressing Modes,”
regarding the region of external data RAM that is addressed by instructions in the MCS 51
architecture.

— Byte register (@Ri, i = 1, 2). Registers R0 and R1 indirectly address on-chip memory

locations 00H–FFH and the lowest 256 bytes of external data RAM. 

— 16-bit data pointer (@DPTR or @A+DPTR). The MOVC and MOVX instructions use

these indirect modes to access code memory and external data RAM.

— 16-bit program counter (@A+PC). The MOVC instruction uses this indirect mode to

access code memory.

Register

00H

–

1FH

R0–R7
(Bank selected by PSW)

Immediate

Operand in Instruction

#data = #00H

–

#FFH

Direct 

00H

–

7FH dir8 

= 

00H

–

7FH

On-chip RAM

SFRs

dir8 = 80H

–

FFH

or SFR mnemonic.

SFR address

 Indirect

00H–FFH

@R0, @R1

Accesses on-chip RAM or the 
lowest 256 bytes of external 
data memory (MOVX).

0000H–FFFFH

@DPTR, @A+DPTR

Accesses external data 
memory (MOVX).

0000H–FFFFH

@A+DPTR, @A+PC

Accesses region FF: of code 
memory (MOVC).