Intel 8XC251SP User Manual
8XC251SA, SB, SP, SQ USER’S MANUAL
5-16
RETI (Return from Interrupt) provides a return from an interrupt service routine. The operation
of RETI depends on the INTR bit in the UCONFIG1 or CONFIG1 configuration byte:
of RETI depends on the INTR bit in the UCONFIG1 or CONFIG1 configuration byte:
•
For INTR = 0, an interrupt pushes the two lower bytes of the PC onto the stack in the
following order: PC.7:0, PC.15:8. The RETI instruction pops these two bytes and uses them
as the 16-bit return address in region FF:. RETI also restores the interrupt logic to accept
additional interrupts at the same priority level as the one just processed.
following order: PC.7:0, PC.15:8. The RETI instruction pops these two bytes and uses them
as the 16-bit return address in region FF:. RETI also restores the interrupt logic to accept
additional interrupts at the same priority level as the one just processed.
•
For INTR = 1, an interrupt pushes the three PC bytes and PSW1 onto the stack in the
following order: PSW1, PC.23:16, PC.7:0, PC.15:8. The RETI instruction pops these four
bytes and then returns to the specified 24-bit address, which can be anywhere in the 16-
Mbyte address space. RETI also clears the interrupt request line. (See the note in Table 5-8
regarding compatibility with code written for MCS 51 microcontrollers.)
following order: PSW1, PC.23:16, PC.7:0, PC.15:8. The RETI instruction pops these four
bytes and then returns to the specified 24-bit address, which can be anywhere in the 16-
Mbyte address space. RETI also clears the interrupt request line. (See the note in Table 5-8
regarding compatibility with code written for MCS 51 microcontrollers.)
The TRAP instruction is useful for the development of emulations of an MCS 251 microcontrol-
ler.
ler.
5.6
PROGRAM STATUS WORDS
The Program Status Word (PSW) register and the Program Status Word 1 (PSW1) register contain
four types of bits (Figures 5-2 and 5-3):
four types of bits (Figures 5-2 and 5-3):
•
CY, AC, OV, N, and Z are flags set by hardware to indicate the result of an operation.
•
The P bit indicates the parity of the accumulator.
•
Bits RS0 and RS1 are programmed by software to select the active register bank for
registers R0–R7.
registers R0–R7.
•
F0 and UD are available to the user as general-purpose flags.
The PSW and PSW1 registers are read/write registers; however, the parity bit in the PSW is not
affected by a write. Individual bits can be addressed with the bit instructions (section 5.4, “Bit
Instructions”). The PSW and PSW1 bits are used implicitly in the conditional jump instructions
(section 5.5.2, “Conditional Jumps”).
affected by a write. Individual bits can be addressed with the bit instructions (section 5.4, “Bit
Instructions”). The PSW and PSW1 bits are used implicitly in the conditional jump instructions
(section 5.5.2, “Conditional Jumps”).
The PSW register is identical to the PSW register in MCS 51 microcontrollers. The PSW1 regis-
ter exists only in MCS 251 microcontrollers. Bits CY, AC, RS0, RS1, and OV in PSW1 are iden-
tical to the corresponding bits in PSW; i.e., the same bit can be accessed in either register. Table
5-10 lists the instructions that affect the CY, AC, OV, N, and Z bits.
ter exists only in MCS 251 microcontrollers. Bits CY, AC, RS0, RS1, and OV in PSW1 are iden-
tical to the corresponding bits in PSW; i.e., the same bit can be accessed in either register. Table
5-10 lists the instructions that affect the CY, AC, OV, N, and Z bits.