Intel 249323-003 User Manual
LXD9785 PQFP Demo Board with FPGA for SS-SMII (Fiber)-to-MII Conversion
Development Kit Manual
31
Document #: 249323
Revision #: 003
Rev. Date: January 24, 2002
Revision #: 003
Rev. Date: January 24, 2002
Figure 16. Clock Distribution
A
A
B
B
C
C
D
D
E
E
4
4
3
3
2
2
1
1
DISTRIBUT
E
*
*
N
O
T
E
*
*
D
U
R
I
N
G
L
AY
O
U
T
T
H
E
S
E
N
E
T
S
M
U
S
T
H
A
V
E
C
ON
T
R
O
L
L
E
D
I
M
P
E
D
A
N
C
E
S
O
F
5
0
O
H
M
S
CLOCK DISTRIBUTION
A
2
L
X
D
97
85
S
S
/S
M
II
M
II
F
X
D
V
B
O
A
R
D
B
14
18
Wednesday, February 21, 2001
Title
Size
Document Number
R
ev
Date:
S
he
et
of
VCCX
SECTION
PLD2_TDI
REF_CLK_0
REF_CLK_2
REF_CLK_1
REF_CLK_3
SECTION
REF_CLK_1
REF_CLK_3
REF_CLK_2
REF_CLK_0
PLD2_T
M
S
PLD2_T
M
S
PLD2_TDO
PLD2_TCK
PLD2_TDI
PLD2_TCK
PLD2_TDO
VCCX
SECTION
3
REF_CLK_1
3
REF_CLK_3
13
REF_CLK_2
13
REF_CLK_0
3
GND
VCC_
E
X
T
GND
GND
GND
GND
GND
VCC_
E
X
T
VCC_EX
T
VCC_EX
T
GND
GND
GND
GND
GND
TP
70
1
TP
71
1
TP
68
1
C156
0.1uF
C157
0.01uF
Y1
125 MHzCRYSTAL OSC
1
7
8
14
NC
GND
OUT
VCC
R454
50 1%
FB8
Ferrite Bead
C349
0.1uF
C348
0.01uF
C346
0.01uF
C347
0.1uF
R736
1K
J5
SMA(5 PIN)
R735
1K
J4
SMA(5 PIN)
R734
1K
R733
1K
R455
50 1%
R456
50 1%
R460
50 1%
TP
62
1
R461
50 1%
TP
63
1
JP14
HEADER 5X2
12
34
56
78
91
0
TP64
1
C350
0.1uF
TP69
1
C351
0.01uF
TP65
1
Y2
125 MHzCRYSTAL OSC
1
7
8
14
NC
GND
OUT
VCC
TP66
1
R732
50 1%
TP
67
1
U46
EPM7032AETC44-4_CLK
_DISTR
1
4
7
9
17
18
20
24
26
29
32
36
37
38
39
40
41
42
16
15
19
TDI
GNDIO
TMS
VCCIO
VCCINT
CLK_OUT1
CLK_OUT3
GNDIO
TCK
VCCIO
TDO
GNDINT
CLK1
INPUT1
INPUT2
CLK2
VCCINT
SECTION
GNDINT
CLK_OUT0
CLK_OUT2