Renesas 16-bit single-chip microcomputer User Manual

A-1

Table of Contents

SFR Page Reference ............................................................................................................ B-1

1. Overview ............................................................................................................................... 1

1.1 Applications .................................................................................................................................................. 1

1.2 Performance Outline .................................................................................................................................... 2

1.3 Block Diagram .............................................................................................................................................. 4

1.4 Product List .................................................................................................................................................. 5

1.5 Pin Configuration ......................................................................................................................................... 6

1.6 Pin Description ............................................................................................................................................. 8

2. Central Processing Unit (CPU) ........................................................................................... 10

2.1 Data Registers (R0, R1, R2, and R3) ........................................................................................................ 10

2.2 Address Registers (A0 and A1) .................................................................................................................. 10

2.3 Frame Base Register (FB) ......................................................................................................................... 11

2.4 Interrupt Table Register (INTB) .................................................................................................................. 11

2.5 Program Counter (PC) ............................................................................................................................... 11

2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) ........................................................................... 11

2.7 Static Base Register (SB) .......................................................................................................................... 11

2.8 Flag Register (FLG) ................................................................................................................................... 11

2.8.1 Carry Flag (C Flag) ............................................................................................................................ 11

2.8.2 Debug Flag (D Flag) .......................................................................................................................... 11

2.8.3 Zero Flag (Z Flag) .............................................................................................................................. 11

2.8.4 Sign Flag (S Flag) .............................................................................................................................. 11

2.8.5 Register Bank Select Flag (B Flag) .................................................................................................... 11

2.8.6 Overflow Flag (O Flag) ....................................................................................................................... 11

2.8.7 Interrupt Enable Flag (I Flag) ............................................................................................................. 11

2.8.8 Stack Pointer Select Flag (U Flag) ..................................................................................................... 11

2.8.9 Processor Interrupt Priority Level (IPL) .............................................................................................. 11

2.8.10 Reserved Area ................................................................................................................................. 11

3. Memory ............................................................................................................................... 12

4. Special Function Register (SFR) ......................................................................................... 13

5. Reset ................................................................................................................................... 25

5.1 Hardware Reset ......................................................................................................................................... 25

5.1.1 Reset on a Stable Supply Voltage ..................................................................................................... 25

5.1.2 Power-on Reset ................................................................................................................................. 25

5.2 Software Reset .......................................................................................................................................... 25

5.3 Watchdog Timer Reset ............................................................................................................................... 25

5.4 Oscillation Stop Detection Reset ............................................................................................................... 25

6. Processor Mode .................................................................................................................. 28

7. Clock Generating Circuit ..................................................................................................... 31

7.1 Types of Clock Generating Circuit ............................................................................................................. 31

7.1.1 Main Clock ......................................................................................................................................... 39

7.1.2 Sub Clock ........................................................................................................................................... 40

7.1.3 On-chip Oscillator Clock .................................................................................................................... 41

7.1.4 PLL Clock ........................................................................................................................................... 41