Fujitsu FR81S User Manual

Page of 2342
FUJITSU SEMICONDUCTOR 
CONTROLLER MANUAL 
MN705-00010-1v0-E 
 
 
 
 
 
FUJITSU SEMICONDUCTOR CONFIDENTIAL 
 
 
 
 
 
 
FR81S 
32-BIT MICROCONTROLLER 
MB91520 Series 
HARDWARE MANUAL 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Following URL introduces the information for effective development of Fujitsu Semiconductor microcontrollers. 
Helpful information is being released for the customers who are considering, or have adopted our 
microcontrollers. 
http://edevice.fujitsu.com/micom/en-support/ 
 
 
 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
 

Summary of Contents of user manual for Fujitsu FR81S

  • Page 1FUJITSU SEMICONDUCTOR MN705-00010-1v0-E CONTROLLER MANUAL FR81S 32-BIT MICROCONTROLLER MB91520 Series HARDWARE MANUAL Following URL introduces the information for effective development...
  • Page 2FUJITSU SEMICONDUCTOR CONFIDENTIAL
  • Page 3 MB91520 Series Preface Thank you for your continued use of Fujitsu semiconductor products. Read this manual and "Data Sheet"...
  • Page 4 MB91520 Series • The contents of this document are subject to change without notice. Customers are advised to consult...
  • Page 5 MB91520 Series How to Use This Manual  Finding a function The following methods can be used to search...
  • Page 6 MB91520 Series Term Explanation 32-bit peripheral A 32-bit width, low-speed internal bus. bus It connects to various types of...
  • Page 7 MB91520 Series Term Explanation SSCG mean "Spread Spectrum Clock Generator". When the clock in electronic equipment generates a single...
  • Page 8 MB91520 Series  Access Unit and Address Position Offset Register name Read only Readable/Writable Address offset value/Register name Address...
  • Page 9 MB91520 Series  Access Unit and Bit Position Register name Register abbreviation Target peripheral function Address Access unit 4.3...
  • Page 10 MB91520 Series  Meaning of Bit Attribute Symbols R : Read enabled W : Write enabled RM : Reading...
  • Page 11 MB91520 Series CONTENTS CHAPTER 1: OVERVIEW ....................................................................................................................... 1 1. OVERVIEW ...................................................................................................................................... 2 2. FEATURES ....................................................................................................................................... 3 2.1. FR81S CPU...
  • Page 12 MB91520 Series 8.2. System Register..............................................................................................................115 9. RESET AND EIT PROCESSING........................................................................................................116 9.1. Reset ...............................................................................................................................117 9.2. EIT Processing................................................................................................................118 9.3. Vector Table...
  • Page 13 MB91520 Series 4.12. PLL/SSCG Output Clock Division Setting Register : CCPSDIVR (CCtl Pll/Sscg clock DIVision Register)......................................................................................................... 191 4.13. PLL...
  • Page 14 MB91520 Series CHAPTER 7: RESET .......................................................................................................................... 255 1. OVERVIEW .................................................................................................................................. 256 2. FEATURES ................................................................................................................................... 257 3. CONFIGURATION .......................................................................................................................... 258...
  • Page 15 MB91520 Series 4.7.DMA Transfer Suppression NMI Flag Register : DNMIR (DMA-halt by NMI Register) . 321 4.8.DMA Transfer Suppression...
  • Page 16 MB91520 Series CHAPTER 11: I/O PORTS .................................................................................................................. 397 1. OVERVIEW .................................................................................................................................. 398 2. FEATURES ................................................................................................................................... 399 3. CONFIGURATION .............................................................................................................................
  • Page 17 MB91520 Series 2. FEATURES ................................................................................................................................... 465 3. CONFIGURATION .......................................................................................................................... 466 4. REGISTERS ................................................................................................................................. 467 4.1. Interrupt Control Registers 00...
  • Page 18 MB91520 Series 4.6.Interrupt Request Batch Read Register 3 lower-order : IRPR3L (Interrupt Request Peripheral Read register 3L) ........................................................................................ 516...
  • Page 19 MB91520 Series 4.2.PPG Cycle Setting Register : PCSR0 to PCSR47 ........................................................ 561 4.3.PPG Duty Setting Register : PDUT0 to...
  • Page 20 MB91520 Series 5.2.2. Activation .................................................................................................................................................. 632 5.2.3. Operation .................................................................................................................................................. 633 6. USAGE EXAMPLE ......................................................................................................................... 634 CHAPTER 19: BASE TIMER...
  • Page 21 MB91520 Series 5.6.6. Application Notes ..................................................................................................................................... 713 5.7. 16/32-bit PWC Timer Operation..................................................................................... 714 5.7.1. Overview ................................................................................................................................................... 716 5.7.2. Operation...
  • Page 22 MB91520 Series 4.1.2. Timer Control Register (Lower Bit) : TCCSL ....................................................................................... 809 4.1.3. Compare Clear Register : CPCLR ...........................................................................................................
  • Page 23 MB91520 Series CHAPTER 23: 32-BIT INPUT CAPTURE ........................................................................................... 877 1. OVERVIEW .................................................................................................................................. 878 2. FEATURES ................................................................................................................................... 879 3. CONFIGURATION...
  • Page 24 MB91520 Series 2. FEATURES ................................................................................................................................... 959 3. CONFIGURATION DIAGRAM ........................................................................................................... 960 4. REGISTERS ................................................................................................................................. 961 4.1. 16-bit Output Compare...
  • Page 25 MB91520 Series 7. Q&A ......................................................................................................................................... 1057 7.1. How to Set the 0.5 Second Count Interval? ................................................................ 1058 7.2. How...
  • Page 26 MB91520 Series 5.3.6. Effect of Sleep Mode ............................................................................................................................. 1113 5.4. Standby Mode : Watch Mode ........................................................................................... 1114 5.4.1. Configuration...
  • Page 27 MB91520 Series 4.3. Wild Register Data Register 00 to 15 : WRDR00 to 15 (Wild Register Data Register 00...
  • Page 28 MB91520 Series CHAPTER 37: BUS PERFORMANCE COUNTERS ........................................................................ 1251 1. OVERVIEW ................................................................................................................................ 1252 2. FEATURES ................................................................................................................................. 1253 3. CONFIGURATION...
  • Page 29 MB91520 Series CHAPTER 40:MULTI-FUNCTION SERIAL INTERFACE................................................................. 1315 1. OVERVIEW ................................................................................................................................ 1316 2. FEATURES ................................................................................................................................. 1317 3. CONFIGURATION ........................................................................................................................ 1324...
  • Page 30 MB91520 Series 4.5.7. Serial Timer Compare Register: STMCR ........................................................................................... 1447 4.5.8. 7-bit Slave Address Mask Register: ISMK ......................................................................................... 1448...
  • Page 31 MB91520 Series 7.2.2. Reception Interrupts and Flag Setting Timing in Assist Mode ......................................................... 1570 7.2.3. Reception Interrupts and Flag...
  • Page 32 MB91520 Series 4.2.5. CAN Interrupt Register : INTR ............................................................................................................. 1717 4.2.6. CAN Test Register : TESTR ................................................................................................................. 1718 4.2.7....
  • Page 33 MB91520 Series 2. FEATURES ................................................................................................................................. 1797 3. CONFIGURATION ........................................................................................................................ 1798 4. REGISTERS ............................................................................................................................... 1799 4.1. DA Control Register :...
  • Page 34 MB91520 Series 5.2.14. High priority activation request operation of other activation channel during the scan conversion ... ......................................................................................................................................................................... ....................................................................................................................................................................
  • Page 35 MB91520 Series 3.2. Sector Configuration Diagram ......................................................................................... 1978 4. REGISTERS ............................................................................................................................... 1979 4.1. WorkFlash Control Register : DFCTLR (WorkFlash...
  • Page 36 MB91520 Series 4.1.1. 16-bit Dead Timer Register (TMRR) ................................................................................................... 2054 4.1.2. 16-bit Dead Timer State Control Register (DTSCR) ............................................................................
  • Page 37 MB91520 Series 1. OVERVIEW ................................................................................................................................ 2170 2. FEATURES ................................................................................................................................. 2171 3. CONFIGURATION ........................................................................................................................ 2172 4. REGISTERS ............................................................................................................................... 2173 4.1....
  • Page 38 MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED (36) CONTENTS FUJITSU SEMICONDUCTOR CONFIDENTIAL
  • Page 39: CHAPTER 1: OVERVIEWCHAPTER 1: OVERVIEW 1. Overview MB91520 Series CHAPTER : OVERVIEW This chapter explains the overview. 1. Overview 2. Features 3....
  • Page 40CHAPTER 1: OVERVIEW 1. Overview MB91520 Series 1. Overview This section explains overview of MB91520 series. MB91520 series is Fujitsu...
  • Page 41CHAPTER 1: OVERVIEW 2. Features MB91520 Series 2. Features This section explains features of MB91520 series. MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED...
  • Page 42CHAPTER 1: OVERVIEW 2. Features MB91520 Series 2.1. FR81S CPU Core FR81S CPU core is shown.  32-bit RISC, load/store...
  • Page 43CHAPTER 1: OVERVIEW 2. Features MB91520 Series 2.2. Peripheral Functions Peripheral functions is shown.  Clock generation (equipped with SSCG...
  • Page 44CHAPTER 1: OVERVIEW 2. Features MB91520 Series  Multi-function serial communication (built-in transmission/reception FIFO memory ) : Max. 12 channels...
  • Page 45CHAPTER 1: OVERVIEW 2. Features MB91520 Series  Real-time clock (RTC) (for day, hours, minutes, seconds)  Main oscillation /...
  • Page 46CHAPTER 1: OVERVIEW 3. Product Line-up MB91520 Series 3. Product Line-up This section shows product line-up of MB91520 series. Table...
  • Page 47CHAPTER 1: OVERVIEW 3. Product Line-up MB91520 Series MB91F522B MB91F523B MB91F524B MB91F525B MB91F526B Low-voltage detection reset Yes Flash Security Yes...
  • Page 48CHAPTER 1: OVERVIEW 3. Product Line-up MB91520 Series Table 3-2 Product Line-up (80 pin) MB91F522D MB91F523D MB91F524D MB91F525D MB91F526D System...
  • Page 49CHAPTER 1: OVERVIEW 3. Product Line-up MB91520 Series MB91F522D MB91F523D MB91F524D MB91F525D MB91F526D Memory Protection Function (MPU) Yes Floating-point arithmetic...
  • Page 50CHAPTER 1: OVERVIEW 3. Product Line-up MB91520 Series Table 3-3 Product Line-up (100 pin) MB91F522F MB91F523F MB91F524F MB91F525F MB91F526F System...
  • Page 51CHAPTER 1: OVERVIEW 3. Product Line-up MB91520 Series MB91F522F MB91F523F MB91F524F MB91F525F MB91F526F Memory Protection Function (MPU) Yes Floating-point arithmetic...
  • Page 52CHAPTER 1: OVERVIEW 3. Product Line-up MB91520 Series Table 3-4 Product Line-up (120 pin) MB91F522J MB91F523J MB91F524J MB91F525J MB91F526J System...
  • Page 53CHAPTER 1: OVERVIEW 3. Product Line-up MB91520 Series MB91F522J MB91F523J MB91F524J MB91F525J MB91F526J Memory Protection Function (MPU) Yes Floating-point arithmetic...
  • Page 54CHAPTER 1: OVERVIEW 3. Product Line-up MB91520 Series Table 3-5 Product Line-up (144 pin) MB91F522K MB91F523K MB91F524K MB91F525K MB91F526K System...
  • Page 55CHAPTER 1: OVERVIEW 3. Product Line-up MB91520 Series MB91F522K MB91F523K MB91F524K MB91F525K MB91F526K Memory Protection Function (MPU) Yes Floating-point arithmetic...
  • Page 56CHAPTER 1: OVERVIEW 3. Product Line-up MB91520 Series Table 3-6 Product Line-up (176 pin) MB91F522L MB91F523L MB91F524L MB91F525L MB91F526L System...
  • Page 57CHAPTER 1: OVERVIEW 3. Product Line-up MB91520 Series MB91F522L MB91F523L MB91F524L MB91F525L MB91F526L Memory Protection Function (MPU) Yes Floating-point arithmetic...
  • Page 58CHAPTER 1: OVERVIEW 4. Function overview MB91520 Series 4. Function overview This section shows function overview of MB91520 series. Table...
  • Page 59CHAPTER 1: OVERVIEW 4. Function overview MB91520 Series Function Features 16-bit/32-bit capture registers to detect a rising edge, a falling...
  • Page 60CHAPTER 1: OVERVIEW 4. Function overview MB91520 Series Function Features With built-in A/D converter 2 units of resolution in 12-bit...
  • Page 61CHAPTER 1: OVERVIEW 4. Function overview MB91520 Series Function Features Reset/interrupt generation at external low-voltage detection External low-voltage detection When...
  • Page 62CHAPTER 1: OVERVIEW 5. Block Diagram MB91520 Series 5. Block Diagram This section shows block diagram of MB91520 series. ...
  • Page 63CHAPTER 1: OVERVIEW 5. Block Diagram MB91520 Series  MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D Regulator FR81s CPU core Power-on rset...
  • Page 64CHAPTER 1: OVERVIEW 5. Block Diagram MB91520 Series  MB91F522F, MB91F523F, MB91F524F, MB91F525F, MB91F526F Regulator FR81s CPU core Power-on rset...
  • Page 65CHAPTER 1: OVERVIEW 5. Block Diagram MB91520 Series  MB91F522J, MB91F523J, MB91F524J, MB91F525J, MB91F526J Regulator FR81s CPU core Power-on rset...
  • Page 66CHAPTER 1: OVERVIEW 5. Block Diagram MB91520 Series  MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K Regulator FR81s CPU core Power-on rset...
  • Page 67CHAPTER 1: OVERVIEW 5. Block Diagram MB91520 Series  MB91F522L, MB91F523L, MB91F524L, MB91F525L, MB91F526L Regulator FR81s CPU core Power-on rset...
  • Page 68CHAPTER 1: OVERVIEW 6. Memory Map MB91520 Series 6. Memory Map This section shows memory map of MB91520 series. Figure...
  • Page 69CHAPTER 1: OVERVIEW 6. Memory Map MB91520 Series Figure 6-2 Memory Map MB91F525, MB91F526 MB91F525 MB91F526 0000 0000H 0000 0000H...
  • Page 70CHAPTER 1: OVERVIEW 7. Pin Assignment MB91520 Series 7. Pin Assignment This section shows pin assignment of MB91520 series. ...
  • Page 71CHAPTER 1: OVERVIEW 7. Pin Assignment MB91520 Series  Pin Assignment MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D 79 P011/WOT/SOT2_1/TIOA0_0/INT3_1 77 P005/SCK2_0/ADTG0_1/INT7_1...
  • Page 72CHAPTER 1: OVERVIEW 7. Pin Assignment MB91520 Series  Pin Assignment MB91F522F, MB91F523F, MB91F524F, MB91F525F, MB91F526F 90 P134/RX2(64)/SCS1_1/ICU7_0/INT7_0 99 P011/WOT/SOT2_1/TIOA0_0/INT3_1...
  • Page 73CHAPTER 1: OVERVIEW 7. Pin Assignment MB91520 Series  Pin Assignment MB91F522J, MB91F523J, MB91F524J, MB91F525J, MB91F526J 107 P134/RX2(64)/SCS1_1/ICU7_0/INT7_0 119 P011/WOT/SOT2_1/TIOA0_0/INT3_1...
  • Page 74CHAPTER 1: OVERVIEW 7. Pin Assignment MB91520 Series  Pin Assignment MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K 140 P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1 127 P134/RX2(64)/SCS1_1/ICU7_0/INT7_0...
  • Page 75CHAPTER 1: OVERVIEW 7. Pin Assignment MB91520 Series  Pin Assignment MB91F522L, MB91F523L, MB91F524L, MB91F525L, MB91F526L 171 P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1 155 P134/RX2(64)/SCS1_1/ICU7_0/INT7_0...
  • Page 76CHAPTER 1: OVERVIEW 8. Device Package MB91520 Series 8. Device Package This section explains device package of MB91520 series. Figure...
  • Page 77CHAPTER 1: OVERVIEW 8. Device Package MB91520 Series Figure 8-2 LQFP-80(FPT-80P-M21) External Dimensions 80-pin plastic LQFP Lead pitch 0.50 mm...
  • Page 78CHAPTER 1: OVERVIEW 8. Device Package MB91520 Series Figure 8-3 LQFP-100(FPT-100P-M20) External Dimensions 100-pin plastic LQFP Lead pitch 0.50 mm...
  • Page 79CHAPTER 1: OVERVIEW 8. Device Package MB91520 Series Figure 8-4 LQFP-120(FPT-120P-M21) External Dimensions 120-pin plastic LQFP Lead pitch 0.50 mm...
  • Page 80CHAPTER 1: OVERVIEW 8. Device Package MB91520 Series Figure 8-5 LQFP-144(FPT-144P-M08) External Dimensions 144-pin plastic LQFP Lead pitch 0.50 mm...
  • Page 81CHAPTER 1: OVERVIEW 8. Device Package MB91520 Series Figure 8-6 LQFP-144(FPT-144P-M12) External Dimensions 144-pin plastic LQFP Lead pitch 0.40 mm...
  • Page 82CHAPTER 1: OVERVIEW 8. Device Package MB91520 Series Figure 8-7 LQFP-176(FPT-176P-M07) External Dimensions 176-pin plastic LQFP Lead pitch 0.50 mm...
  • Page 83 CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9. Explanation of Pin Functions The pin function list...
  • Page 84 CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Number I/O Function Polarity Pin Name circuit (Please...
  • Page 85 CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Number I/O Function Polarity Pin Name circuit (Please...
  • Page 86 CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Number I/O Function Polarity Pin Name circuit (Please...
  • Page 87 CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Number I/O Function Polarity Pin Name circuit (Please...
  • Page 88 CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Number I/O Function Polarity Pin Name circuit (Please...
  • Page 89 CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Number I/O Function Polarity Pin Name circuit (Please...
  • Page 90 CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Number I/O Function Polarity Pin Name circuit (Please...
  • Page 91 CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Number I/O Function Polarity Pin Name circuit (Please...
  • Page 92 CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Number I/O Function Polarity Pin Name circuit (Please...
  • Page 93 CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Number I/O Function Polarity Pin Name circuit (Please...
  • Page 94CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1. Pins of Each Function Pins of each function are...
  • Page 95CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.1. Pins of A/D converter (ch.0 to ch.47) Pin Noise...
  • Page 96CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Noise Pin Number Function Name Filter 64 80 100...
  • Page 97CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.2. Pins of CAN (ch.0 to ch.2) Pin Noise Pin...
  • Page 98CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.3. Pins of D/A converter (ch.0 to ch.1) Pin Noise...
  • Page 99CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.4. Pins of External interrupt input Pin Noise Pin Number...
  • Page 100CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.5. Pins of Multi-function serial interface (ch.0 to ch.11) Pin...
  • Page 101CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Noise Pin Number Function Name Filter 64 80 100...
  • Page 102CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.6. Pins of PPG (ch.0 to ch.47) Pin Noise Pin...
  • Page 103CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Noise Pin Number Function Name Filter 64 80 100...
  • Page 104CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Noise Pin Number Function Name Filter 64 80 100...
  • Page 105CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.7. Pin of RTC Pin Noise Pin Number Function Name...
  • Page 106CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.8. Pins of Up/down counter Pin Noise Pin Number Function...
  • Page 107CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.9. Pins of Output compare (ch.0 to ch.5: 16bit, ch.6...
  • Page 108CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.10. Pins of Input capture (ch.0 to ch.3: 16bit, ch.4...
  • Page 109CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.11. Pins of Free-run timer (ch.0 to ch.2: 16bit, ch.3...
  • Page 110CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.12. Pins of Base timer (ch.0, ch.1) Pin Noise Pin...
  • Page 111CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.13. Pins of Reload timer (ch.0 to ch.7) Pin Noise...
  • Page 112CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.14. Pins of External Bus interface Pin Noise Pin Number...
  • Page 113CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Noise Pin Number Function Name Filter 64 80 100...
  • Page 114CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.15. Pins of Waveform generator (ch.0 to ch.5) Pin Noise...
  • Page 115CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.16. Pin of Clock monitor Pin Noise Pin Number Function...
  • Page 116CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.17. Pins of Port Function (General-Purpose I/O) Pin Noise Pin...
  • Page 117CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Noise Pin Number Function Name Filter 64 80 100...
  • Page 118CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Noise Pin Number Function Name Filter 64 80 100...
  • Page 119CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series Pin Noise Pin Number Function Name Filter 64 80 100...
  • Page 120CHAPTER 1: OVERVIEW 9. Explanation of Pin Functions MB91520 Series 9.1.18. Other Pins Pin Noise Pin Number Function Name Filter...
  • Page 121CHAPTER 1: OVERVIEW 10. I/O Circuit Types MB91520 Series 10. I/O Circuit Types This section shows I/O Circuit Types. Type...
  • Page 122CHAPTER 1: OVERVIEW 10. I/O Circuit Types MB91520 Series Type Circuit Remarks F Pull-up control - General-purpose I/O port Output...
  • Page 123CHAPTER 1: OVERVIEW 10. I/O Circuit Types MB91520 Series Type Circuit Remarks L - Open drain I/O pin - Output...
  • Page 124CHAPTER 1: OVERVIEW 10. I/O Circuit Types MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 86 CHAPTER : OVERVIEW FUJITSU SEMICONDUCTOR CONFIDENTIAL...
  • Page 125: CHAPTER 2: HANDLING THE DEVICECHAPTER 2: HANDLING THE DEVICE 1. Handling Precautions MB91520 Series CHAPTER : HANDLING THE DEVICE This chapter explains the notes...
  • Page 126CHAPTER 2: HANDLING THE DEVICE 1. Handling Precautions MB91520 Series 1. Handling Precautions Any semiconductor devices have inherently a certain...
  • Page 127CHAPTER 2: HANDLING THE DEVICE 1. Handling Precautions MB91520 Series  Observance of Safety Regulations and Standards Most countries in...
  • Page 128CHAPTER 2: HANDLING THE DEVICE 1. Handling Precautions MB91520 Series  Storage of Semiconductor Devices Because plastic chip packages are...
  • Page 129CHAPTER 2: HANDLING THE DEVICE 1. Handling Precautions MB91520 Series Please check the latest handling precautions at the following URL....
  • Page 130CHAPTER 2: HANDLING THE DEVICE 2. Handling Device MB91520 Series 2. Handling Device This section explains the handling device. ...
  • Page 131CHAPTER 2: HANDLING THE DEVICE 2. Handling Device MB91520 Series  Power supply pins The device is designed to ensure...
  • Page 132CHAPTER 2: HANDLING THE DEVICE 2. Handling Device MB91520 Series  Treatment of A/D converter power supply pins Connect the...
  • Page 133CHAPTER 2: HANDLING THE DEVICE 3. Application Notes MB91520 Series 3. Application Notes This section explains application notes. 3.1 Function...
  • Page 134CHAPTER 2: HANDLING THE DEVICE 3. Application Notes MB91520 Series 3.1. Function Switching of a Multiplexed Port Function switching of...
  • Page 135CHAPTER 2: HANDLING THE DEVICE 3. Application Notes MB91520 Series 3.2. Low-power Consumption Mode This section explains low-power consumption mode....
  • Page 136CHAPTER 2: HANDLING THE DEVICE 3. Application Notes MB91520 Series 3.3. Notes When Writing Data in a Register Having the...
  • Page 137: CHAPTER 3: CPUCHAPTER 3: CPU 1. Overview MB91520 Series CHAPTER : CPU This chapter explains the CPU. 1. Overview 2. Features 3....
  • Page 138CHAPTER 3: CPU 1. Overview MB91520 Series 1. Overview This section explains the overview of the CPU. The FR81 architecture...
  • Page 139CHAPTER 3: CPU 2. Features MB91520 Series 2. Features This section explains features of the CPU. The FR family is...
  • Page 140CHAPTER 3: CPU 2. Features MB91520 Series  Floating Point Operations ⋅ IEEE754 compliant ⋅ Support single precision ⋅ Six...
  • Page 141CHAPTER 3: CPU 3. CPU Operating Description MB91520 Series 3. CPU Operating Description This section explains the operation of the...
  • Page 142CHAPTER 3: CPU 3. CPU Operating Description MB91520 Series 3.1. CPU Operating Status The CPU operating status is shown below....
  • Page 143CHAPTER 3: CPU 3. CPU Operating Description MB91520 Series 3.1.1. Reset State The reset state is shown below. The reset...
  • Page 144CHAPTER 3: CPU 3. CPU Operating Description MB91520 Series 3.1.2. Normal Run State The normal run state is shown below....
  • Page 145CHAPTER 3: CPU 3. CPU Operating Description MB91520 Series 3.1.3. Low-power Consumption State The low-power consumption state is shown below....
  • Page 146CHAPTER 3: CPU 3. CPU Operating Description MB91520 Series 3.1.4. Debug Run State The debug run state is shown below....
  • Page 147CHAPTER 3: CPU 4. Pipeline Operation MB91520 Series 4. Pipeline Operation This section explains the pipeline operation of the CPU....
  • Page 148CHAPTER 3: CPU 5. Floating Point Operation Processing MB91520 Series 5. Floating Point Operation Processing The floating point operation processing...
  • Page 149CHAPTER 3: CPU 6. Data Structure MB91520 Series 6. Data Structure This section explains the data structure of the CPU....
  • Page 150CHAPTER 3: CPU 7. Addressing MB91520 Series 7. Addressing This section explains addressing of the CPU. A memory space is...
  • Page 151CHAPTER 3: CPU 8. Programming Model MB91520 Series 8. Programming Model This section explains the programming model of the CPU....
  • Page 152CHAPTER 3: CPU 8. Programming Model MB91520 Series 8.1. General-purpose Registers, Dedicated Registers, and Floating Point Registers This section explains...
  • Page 153CHAPTER 3: CPU 8. Programming Model MB91520 Series 8.2. System Register The system register is shown below. System register is...
  • Page 154CHAPTER 3: CPU 9. Reset and EIT Processing MB91520 Series 9. Reset and EIT Processing The reset is shown below....
  • Page 155CHAPTER 3: CPU 9. Reset and EIT Processing MB91520 Series 9.1. Reset The reset is shown below. Reset forcibly suspends...
  • Page 156CHAPTER 3: CPU 9. Reset and EIT Processing MB91520 Series 9.2. EIT Processing The EIT processing is shown below. The...
  • Page 157CHAPTER 3: CPU 9. Reset and EIT Processing MB91520 Series 9.3. Vector Table The vector table is shown. Table 9-1...
  • Page 158CHAPTER 3: CPU 9. Reset and EIT Processing MB91520 Series Interrupt Vector Address at Number Interrupt Interruption Factor Offset TBR...
  • Page 159CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10. Memory Protection Function (MPU) This section explains the memory...
  • Page 160CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.1. Overview This section explains the overview of memory protection...
  • Page 161CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.2. List of Registers The list of registers is shown....
  • Page 162CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.3. Description of Registers Registers are shown. 10.3.1. MPU Control...
  • Page 163CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.3.1. MPU Control Register : MPUCR The bit configuration of...
  • Page 164CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series [bit12] UIE (User Mode Instruction Fetch Enable) This bit is...
  • Page 165CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series [bit3, bit2] PAN (Protection Area Number) Indicates the number of...
  • Page 166CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.3.2. Instruction Access Protection Violation Address Register : IPVAR The...
  • Page 167CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.3.3. Instruction Access Protection Violation Status Register : IPVSR The...
  • Page 168CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series [bit0] IPV (Instruction fetch Protection Violation) This bit indicates that...
  • Page 169CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.3.4. Data Access Protection Violation Address Register :DPVAR The bit...
  • Page 170CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.3.5. Data Access Protection Violation Status Register : DPVSR The...
  • Page 171CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series [bit5, bit4] SZ[1:0] The access size when the violation occurred....
  • Page 172CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.3.6. Data Access Error Address Register : DEAR The bit...
  • Page 173CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.3.7. Data Access Error Status Register : DESR The bit...
  • Page 174CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series [bit3] MD This bit indicates the mode of the access....
  • Page 175CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.3.8. Protection Area Base Address Register 0 to 7 :...
  • Page 176CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.3.9. Protection Area Control Register 0 to 7 : PACR0...
  • Page 177CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series [bit12] UIE (User Mode Instruction Fetch Enable) This bit is...
  • Page 178CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series Size of the specified ASZ[4:0] protectorate area 00010B Reserved 00011B...
  • Page 179CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series [bit0] PAE (Protection Area Enable) This bit is for enabling...
  • Page 180CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.4. Operations of Memory Protection Function The memory protection function...
  • Page 181CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.4.1. Setting Up Memory Protection Areas The setting up memory...
  • Page 182CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.4.2. Instruction Access Protection Violation The instruction access protection violation...
  • Page 183CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.4.3. Data Access Protection Violation The data access protection violation...
  • Page 184CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.4.4. Data Access Errors This section explains data access errors...
  • Page 185CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.4.5. Memory Protection Operation by Delay Slot The memory protection...
  • Page 186CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.4.6. DEAR and DESR Update The DEAR and the DESR...
  • Page 187CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series 10.4.7. Notes This section explains notes of the Memory Protection...
  • Page 188CHAPTER 3: CPU 10. Memory Protection Function (MPU) MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 150 CHAPTER : CPU FUJITSU SEMICONDUCTOR...
  • Page 189: CHAPTER 4: OPERATION MODECHAPTER 4: OPERATION MODE 1. Overview MB91520 Series CHAPTER : OPERATION MODE This chapter explains the operation mode. 1. Overview...
  • Page 190CHAPTER 4: OPERATION MODE 1. Overview MB91520 Series 1. Overview This section explains the overview of the operation mode. This...
  • Page 191CHAPTER 4: OPERATION MODE 2. Features MB91520 Series 2. Features This section explains features of the operation mode. This device...
  • Page 192CHAPTER 4: OPERATION MODE 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the operation mode. Figure...
  • Page 193CHAPTER 4: OPERATION MODE 4. Register MB91520 Series 4. Register This section explains the register of the operation mode. Register...
  • Page 194CHAPTER 4: OPERATION MODE 4. Register MB91520 Series 4.1. Bus Mode Register : BMODR (Bus MODe Register) The bit configuration...
  • Page 195CHAPTER 4: OPERATION MODE 5. Operation MB91520 Series 5. Operation This section explains operations of the operation mode. 5.1. MD0,...
  • Page 196CHAPTER 4: OPERATION MODE 5. Operation MB91520 Series 5.1. MD0, MD1, P006 Pins Settings MD0, MD1 and P006 pins settings...
  • Page 197CHAPTER 4: OPERATION MODE 5. Operation MB91520 Series 5.2. Fetching the Operation Mode The fetching the operation mode is shown....
  • Page 198CHAPTER 4: OPERATION MODE 5. Operation MB91520 Series 5.3. Explanation of Each Operation Mode The each operation mode is shown....
  • Page 199CHAPTER 4: OPERATION MODE 5. Operation MB91520 Series 5.3.1. User Mode The user mode is shown. An external bus pin...
  • Page 200CHAPTER 4: OPERATION MODE 5. Operation MB91520 Series 5.3.2. Serial Writer Mode The serial writer mode is shown. Contact their...
  • Page 201: CHAPTER 5: CLOCKCHAPTER 5: CLOCK 1. Overview MB91520 Series CHAPTER : CLOCK This chapter explains the clock. 1 Overview 2 Features 3...
  • Page 202CHAPTER 5: CLOCK 1. Overview MB91520 Series 1. Overview This section explains the overview of the clock. The built-in oscillation...
  • Page 203CHAPTER 5: CLOCK 1. Overview MB91520 Series Figure 1-1 Diagram of the Clock Generation System Main clock (MCLK) PLL clock...
  • Page 204CHAPTER 5: CLOCK 2. Features MB91520 Series 2. Features This section explains features of the clock. ⋅ 2 system on-chip...
  • Page 205CHAPTER 5: CLOCK 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the clock. Figure 3-1 Connection...
  • Page 206CHAPTER 5: CLOCK 3. Configuration MB91520 Series Figure 3-3 Connection Diagram of Clock (1)-3 PLL/SSCG Clock Generation Unit CSELR. PLLCR....
  • Page 207CHAPTER 5: CLOCK 3. Configuration MB91520 Series Figure 3-5 Connection Diagram of Clock (3) Divider Control Peripheral clock divider control...
  • Page 208CHAPTER 5: CLOCK 3. Configuration MB91520 Series Figure 3-8 Diagram of the Clock System Regulator FR81s CPU core Power-on rset...
  • Page 209CHAPTER 5: CLOCK 4. Registers MB91520 Series 4. Registers This section explains registers of the clock. Table 4-1 Registers Map...
  • Page 210CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.1. Division Configuration Register 0 : DIVR0 (Division clock configuration Register 0) The...
  • Page 211CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.2. Division Configuration Register 1 : DIVR1 (Division clock configuration Register 1) The...
  • Page 212CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.3. Division Configuration Register 2 : DIVR2 (Division clock configuration Register 2) The...
  • Page 213CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.4. Clock Source Selection Register : CSELR (Clock source Selection Register) The bit...
  • Page 214CHAPTER 5: CLOCK 4. Registers MB91520 Series Note: PLL enters the status of the oscillation enable regardless of the value...
  • Page 215CHAPTER 5: CLOCK 4. Registers MB91520 Series However, when CKS[1:0] ≠ CKM[1:0], these bits cannot be rewritten. When the clock...
  • Page 216CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.5. Clock Source Monitor Register : CMONR (Clock source MONitor Register) The bit...
  • Page 217CHAPTER 5: CLOCK 4. Registers MB91520 Series Note: PCRDY=1 may be read immediately after changing PCEN=1 to 0. PLL enters...
  • Page 218CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.6. Main Timer Control Register : MTMCR (Main clock TiMer Control Register) The...
  • Page 219CHAPTER 5: CLOCK 4. Registers MB91520 Series [bit6] MTIE (Main clock Timer Interrupt Enable) : Main timer interrupt enabled This...
  • Page 220CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.7. Sub Timer Control Register : STMCR (Sub clock TiMer Control Register) The...
  • Page 221CHAPTER 5: CLOCK 4. Registers MB91520 Series [bit6] STIE (Sub clock Timer Interrupt Enable) : Sub timer interrupt enable This...
  • Page 222CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.8. PLL Setting Register : PLLCR (PLL Configuration Register) The bit configuration of...
  • Page 223CHAPTER 5: CLOCK 4. Registers MB91520 Series [bit7 to bit4] POSW[3:0] (Pll clock OSc Wait) : PLL oscillation stabilization wait...
  • Page 224CHAPTER 5: CLOCK 4. Registers MB91520 Series [bit3 to bit0] PDS[3:0] (Pll input clock Divider selection) : PLL input clock...
  • Page 225CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.9. Clock Stabilization Selection Register : CSTBR (Clock STaBilization selection Register) The bit...
  • Page 226CHAPTER 5: CLOCK 4. Registers MB91520 Series [bit3 to bit0] MOSW[3:0] (Main clock OSc Wait) : Main clock oscillation stabilization...
  • Page 227CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.10. PLL Oscillation Timer Control Register : PTMCR (PLL clock osc TiMer Control...
  • Page 228CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.11. PLL/SSCG Clock Selection Register : CCPSSELR (CCtl Pll/Sscg clock Selection Register) The...
  • Page 229CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.12. PLL/SSCG Output Clock Division Setting Register : CCPSDIVR (CCtl Pll/Sscg clock DIVision...
  • Page 230CHAPTER 5: CLOCK 4. Registers MB91520 Series [bit2 to bit0] SODS[2:0] (Sscg Oscillator Divider selection) : SSCG Selection of SSCG...
  • Page 231CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.13. PLL Feedback Division Setting Register : CCPLLFBR (CCtl PLL FB clock division...
  • Page 232CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.14. SSCG Feedback Division Setting Register 0 : CCSSFBR0 (CCtl SScg FB clock...
  • Page 233 CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.15. SSCG Feedback Division Setting Register 1 : CCSSFBR1 (CCtl SScg FB clock...
  • Page 234CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.16. SSCG Configuration Setting Register 0 : CCSSCCR0 (CCtl SSCg Config. Register 0)...
  • Page 235CHAPTER 5: CLOCK 4. Registers MB91520 Series  Center Spread Cycle to cycle jitter modulation rate Target time Period 1/Modulation...
  • Page 236CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.17. SSCG Configuration Setting Register 1 : CCSSCCR1 (CCtl SSCg Config. Register 1)...
  • Page 237 CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.18. Clock Gear Configuration Setting Register 0 : CCCGRCR0 (CCtl Clock Gear Config....
  • Page 238CHAPTER 5: CLOCK 4. Registers MB91520 Series When GRSTS=10 GRSTR Operation "0" write Not affect the operation "1" write Start...
  • Page 239CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.19. Clock Gear Configuration Setting Register 1 : CCCGRCR1 (CCtl Clock Gear Config....
  • Page 240CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.20. Clock Gear Configuration Setting Register 2 : CCCGRCR2 (CCtl Clock Gear Config....
  • Page 241 CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.21. RTC/PMU Clock Selection Register : CCRTSELR (CCtl RTc pmu clock Selection Register)...
  • Page 242CHAPTER 5: CLOCK 4. Registers MB91520 Series Notes: ⋅ It takes main clock × about 3 cycles + sub clock...
  • Page 243CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.22. PMU Clock Division Setting Register 0 : CCPMUCR0 (CCtl PMU Clock division...
  • Page 244CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.23. PMU Clock Division Setting Register 1 : CCPMUCR1 (CCtl PMU Clock division...
  • Page 245CHAPTER 5: CLOCK 4. Registers MB91520 Series Note: Writing to this bit is ignored while CCPMUCR1.GST bit is "1". MN705-00010-1v0-E...
  • Page 246 CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.24. Sync/Async Control Register : SACR The bit configuration of the sync/async control...
  • Page 247CHAPTER 5: CLOCK 4. Registers MB91520 Series 4.25. Peripheral Interface Clock Divider : PICD The bit configuration of peripheral interface...
  • Page 248CHAPTER 5: CLOCK 4. Registers MB91520 Series Note: Set this register so that the peripheral clock (PCLK2) definitely becomes 40MHz...
  • Page 249CHAPTER 5: CLOCK 5. Operation MB91520 Series 5. Operation This section explains operations of clock. 5.1. Oscillation Control 5.2. Oscillation...
  • Page 250CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.1. Oscillation Control This section explains oscillation control. MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 212...
  • Page 251CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.1.1. Main Clock (MCLK) The main clock (MCLK) is shown. The oscillation of...
  • Page 252CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.1.2. Sub Clock (SBCLK) The sub clock (SBCLK) is shown. The oscillation of...
  • Page 253CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.1.3. PLL/SSCG Clock (PLLSSCLK) The PLL/SSCG clock (PLLSSCLK) is shown. This LSI has...
  • Page 254CHAPTER 5: CLOCK 5. Operation MB91520 Series The formula for calculating the clock frequency and the multiplication rate related to...
  • Page 255CHAPTER 5: CLOCK 5. Operation MB91520 Series Notes: ⋅ In debug operation (E_DBCR:PLOCK =1), PLL cannot stop because always supplying...
  • Page 256CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.1.4. Limitations when PLL/SSCG Clock is used The limitations of the PLL/SSCG clock...
  • Page 257CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.2. Oscillation Stabilization Wait Oscillation stabilization wait is shown. This section describes oscillation...
  • Page 258CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.2.1. Conditions for Generating Stabilization Wait Time Conditions for the generating stabilization wait...
  • Page 259CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.2.2. Selecting Stabilization Wait Time Selecting the stabilization wait time is shown. The...
  • Page 260CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.2.3. End of the Stabilization Wait Time The end of the stabilization wait...
  • Page 261CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.3. Selecting the Source Clock (SRCCLK) Selecting the source clock (SRCCLK) is shown....
  • Page 262CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.3.1. Selecting the Source Clock at the Time of Initialization Selecting the source...
  • Page 263CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.3.2. Procedure of switching the source clock The procedure of switching the source...
  • Page 264CHAPTER 5: CLOCK 5. Operation MB91520 Series The clock gear begins (CCCGRCR0.GRSTR=1) ↓ Verifies that the clock gear high-speed oscillation...
  • Page 265CHAPTER 5: CLOCK 5. Operation MB91520 Series Switches the source clock to the sub clock (CSELR.CKS[1:0]=01→11) ↓ While selecting the...
  • Page 266CHAPTER 5: CLOCK 5. Operation MB91520 Series Figure 5-4 Example of PLL/SSCG Mode Setting Main → PLL/SSCG Start Main clock...
  • Page 267CHAPTER 5: CLOCK 5. Operation MB91520 Series Figure 5-5 Example of PLL/SSCG Mode Setting PLL/SSCG → Main Start No CSELR.CKS=10...
  • Page 268CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.4. Timer The timer is shown. MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 230 CHAPTER :...
  • Page 269CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.4.1. Main Clock Oscillation Stabilization Wait Timer (Main Timer) The main clock oscillation...
  • Page 270CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.4.2. Sub Clock Oscillation Stabilization Wait Timer (Sub Timer) The sub clock oscillation...
  • Page 271CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.4.3. PLL/SSCG Clock Oscillation Stabilization Wait timer (PLL Timer) The PLL/SSCG clock oscillation...
  • Page 272CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.4.4. Setting Setting is shown. If the main timer operation is enabled (MTMCR.MTE=1),...
  • Page 273CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.4.5. Procedure for Setting the Timer Interrupt The procedure for setting the timer...
  • Page 274CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.4.6. Timer Operations Timer operations are shown. When MTMCR.MTE=1, the main timer counts...
  • Page 275CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.4.7. Watch Mode and Timer Interrupt Watch mode and timer interrupt are shown....
  • Page 276CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.5. Notes when Clocks Conflict Notes when clocks conflict is shown. Notes that...
  • Page 277CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.6. The Clock Gear Circuit The clock gear circuit is shown. When the...
  • Page 278CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.6.1. Procedure of Gear Up The procedure of gear up is shown. 1....
  • Page 279CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.6.2. Procedure of Gear Down The procedure of gear down is shown. 1....
  • Page 280CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.7. Operations during MDI Communications Operations during MDI communications are shown. The main...
  • Page 281CHAPTER 5: CLOCK 5. Operation MB91520 Series 5.8. About PMU clock (PMUCLK) The PMU clock (PMUCLK) is shown. The PMU...
  • Page 282CHAPTER 5: CLOCK 5. Operation MB91520 Series (2) F-divider must be set so that the PMU clock frequency become 32kHz...
  • Page 283: CHAPTER 6: CLOCK RESET STATE TRANSITIONSCHAPTER 6: CLOCK RESET STATE TRANSITIONS 1. Overview MB91520 Series CHAPTER : CLOCK RESET STATE TRANSITIONS This chapter explains clock...
  • Page 284CHAPTER 6: CLOCK RESET STATE TRANSITIONS 1. Overview MB91520 Series 1. Overview This section explains the overview of clock reset...
  • Page 285CHAPTER 6: CLOCK RESET STATE TRANSITIONS 2. Device States and Transitions MB91520 Series 2. Device States and Transitions This section...
  • Page 286CHAPTER 6: CLOCK RESET STATE TRANSITIONS 2. Device States and Transitions MB91520 Series 2.1. Diagram of State Transitions This section...
  • Page 287CHAPTER 6: CLOCK RESET STATE TRANSITIONS 2. Device States and Transitions MB91520 Series *1 : There is a register not...
  • Page 288CHAPTER 6: CLOCK RESET STATE TRANSITIONS 2. Device States and Transitions MB91520 Series 2.2. Explanation of Each States This section...
  • Page 289CHAPTER 6: CLOCK RESET STATE TRANSITIONS 2. Device States and Transitions MB91520 Series  Main Oscillation Stabilization Wait (Reset) State...
  • Page 290CHAPTER 6: CLOCK RESET STATE TRANSITIONS 2. Device States and Transitions MB91520 Series 2.3. Priority of State Transition Requests Priority...
  • Page 291CHAPTER 6: CLOCK RESET STATE TRANSITIONS 3. Device State and Regulator Mode Corresponding to those MB91520 Series States 3. Device...
  • Page 292CHAPTER 6: CLOCK RESET STATE TRANSITIONS 3. Device State and Regulator Mode Corresponding to those MB91520 Series States Table 3-2...
  • Page 293: CHAPTER 7: RESETCHAPTER 7: RESET 1. Overview MB91520 Series CHAPTER : RESET This chapter explains the reset. 1. Overview 2. Features 3....
  • Page 294CHAPTER 7: RESET 1. Overview MB91520 Series 1. Overview This section explains the overview of the reset. When a reset...
  • Page 295CHAPTER 7: RESET 2. Features MB91520 Series 2. Features This section explains features of the reset. This product, which has...
  • Page 296CHAPTER 7: RESET 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the reset. Figure 3-1 Configuration...
  • Page 297CHAPTER 7: RESET 3. Configuration MB91520 Series Figure 3-2 Configuration Diagram of Reset (Reset Control) Reset request by simultaneously assert...
  • Page 298CHAPTER 7: RESET 4. Registers MB91520 Series 4. Registers This section explains the registers of the reset. Table 4-1 Registers...
  • Page 299 CHAPTER 7: RESET 4. Registers MB91520 Series 4.1. Reset Source Register : RSTRR (ReSeT Result Register) The bit configuration of...
  • Page 300CHAPTER 7: RESET 4. Registers MB91520 Series RSTX pin reset detection, illegal standby mode ERST transition detection, clock supervisor reset...
  • Page 301 CHAPTER 7: RESET 4. Registers MB91520 Series 4.2. Reset Control Register : RSTCR (ReSeT Control Register) The bit configuration of...
  • Page 302 CHAPTER 7: RESET 4. Registers MB91520 Series 4.3. CPU Abnormal Operation Register : CPUAR (CPU Abnormal operation Register) The bit...
  • Page 303CHAPTER 7: RESET 4. Registers MB91520 Series [bit1] PSTF (illegal PLL-run to STandby Flag) : Illegal standby mode transition detection...
  • Page 304CHAPTER 7: RESET 4. Registers MB91520 Series 4.4. PMU Status Register : PMUSTR (Power Management Unit STatus register) The bit...
  • Page 305CHAPTER 7: RESET 5. Operation MB91520 Series 5. Operation This section explains each operation of the reset feature of this...
  • Page 306CHAPTER 7: RESET 5. Operation MB91520 Series 5.1. Reset Level The reset level is explained. The following two levels of...
  • Page 307CHAPTER 7: RESET 5. Operation MB91520 Series 5.1.1. Initialize Reset (INIT) Initialize reset (INIT) is explained. It initializes all register...
  • Page 308CHAPTER 7: RESET 5. Operation MB91520 Series 5.1.2. Reset (RST) The reset (RST) is explained. It initializes the entire hardware...
  • Page 309CHAPTER 7: RESET 5. Operation MB91520 Series 5.2. Reset Factor This section explains each reset factor of this product. 5.2.1....
  • Page 310CHAPTER 7: RESET 5. Operation MB91520 Series 5.2.1. Power-on Reset Power-on reset is shown. It is a reset factor generated...
  • Page 311CHAPTER 7: RESET 5. Operation MB91520 Series 5.2.2. RSTX Pin Input The RSTX pin input is shown. It is a...
  • Page 312CHAPTER 7: RESET 5. Operation MB91520 Series 5.2.3. Watchdog Reset 0 The watchdog reset 0 is shown. It is a...
  • Page 313CHAPTER 7: RESET 5. Operation MB91520 Series 5.2.4. Watchdog Reset 1 The watchdog reset 1 is shown. It is a...
  • Page 314CHAPTER 7: RESET 5. Operation MB91520 Series 5.2.5. External Low-Voltage Detection Reset The external low-voltage detection reset is shown. Low-voltage...
  • Page 315CHAPTER 7: RESET 5. Operation MB91520 Series 5.2.6. Illegal Standby Mode Transition Detection Reset the illegal standby mode transition detection...
  • Page 316CHAPTER 7: RESET 5. Operation MB91520 Series 5.2.7. Internal Low-Voltage Detection Reset The internal low-voltage detection reset is shown. Low-voltage...
  • Page 317CHAPTER 7: RESET 5. Operation MB91520 Series 5.2.8. Flash Security Violation Reset The Flash security violation reset is shown. It...
  • Page 318CHAPTER 7: RESET 5. Operation MB91520 Series 5.2.9. Software Reset (RSTCR:SRST) The software reset (RSTCR:SRST) is shown. It is a...
  • Page 319CHAPTER 7: RESET 5. Operation MB91520 Series 5.2.10. Recovery from Standby (Power Interception) Recovery from standby (power interception) is shown....
  • Page 320CHAPTER 7: RESET 5. Operation MB91520 Series 5.3. Reset Acceptance This section explains the acceptance processing of each reset factor....
  • Page 321CHAPTER 7: RESET 5. Operation MB91520 Series 5.3.1. Generation of Reset Request The generation of a reset request is shown....
  • Page 322CHAPTER 7: RESET 5. Operation MB91520 Series 5.3.2. Acceptance of Reset Request Acceptance of a reset request is shown. Once...
  • Page 323CHAPTER 7: RESET 5. Operation MB91520 Series 5.3.3. Reset Issue Delay Counter The reset issue delay counter is shown. As...
  • Page 324CHAPTER 7: RESET 5. Operation MB91520 Series 5.3.4. Irregular Reset The irregular reset is shown. If a reset is issued...
  • Page 325CHAPTER 7: RESET 5. Operation MB91520 Series 5.4. Reset Issue A reset will be issued after a reset request has...
  • Page 326CHAPTER 7: RESET 5. Operation MB91520 Series 5.4.1. Super Initialize Reset (SINIT) The super initialize reset (SINIT) is shown. The...
  • Page 327CHAPTER 7: RESET 5. Operation MB91520 Series The following describes each reset issue sequence after reset factors of this reset...
  • Page 328CHAPTER 7: RESET 5. Operation MB91520 Series 5.4.2. Initialize Reset (INIT) Initialize reset (INIT) is shown. If a reset factor...
  • Page 329CHAPTER 7: RESET 5. Operation MB91520 Series 5.4.3. Reset (RST) The reset (RST) is shown. If a reset factor that...
  • Page 330CHAPTER 7: RESET 5. Operation MB91520 Series 5.5. Reset Sequence The reset sequence is shown. This product transits from the...
  • Page 331CHAPTER 7: RESET 5. Operation MB91520 Series 5.5.1. Reset Cycle The reset cycle is shown. After the release of reset...
  • Page 332CHAPTER 7: RESET 5. Operation MB91520 Series 5.5.2. Reset Release The reset release is shown. Once a reset cycle has...
  • Page 333CHAPTER 7: RESET 5. Operation MB91520 Series 5.5.3. Operating Mode Fix Operating mode fix is shown. The mode control circuit...
  • Page 334CHAPTER 7: RESET 5. Operation MB91520 Series 5.5.4. Transition of Bus Control Transition of bus control is shown. After the...
  • Page 335CHAPTER 7: RESET 5. Operation MB91520 Series 5.5.5. Reset Vector Fetch Reset vector fetch is shown. After the reset release,...
  • Page 336CHAPTER 7: RESET 5. Operation MB91520 Series 5.5.6. Reset and Forced Break Reset and forced break are shown. If a...
  • Page 337CHAPTER 7: RESET 5. Operation MB91520 Series 5.6. Notes Notes are shown. During return form standby watch mode (power shut-down)...
  • Page 338CHAPTER 7: RESET 5. Operation MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 300 CHAPTER : RESET FUJITSU SEMICONDUCTOR CONFIDENTIAL 47
  • Page 339: CHAPTER 8: DMA CONTROLLER (DMAC)CHAPTER 8: DMA CONTROLLER (DMAC) 1. Overview MB91520 Series CHAPTER : DMA CONTROLLER (DMAC) This chapter explains the DMA controller...
  • Page 340CHAPTER 8: DMA CONTROLLER (DMAC) 1. Overview MB91520 Series 1. Overview This section explains the overview of the DMA controller...
  • Page 341CHAPTER 8: DMA CONTROLLER (DMAC) 2. Features MB91520 Series 2. Features This section explains the features of the DMA controller...
  • Page 342CHAPTER 8: DMA CONTROLLER (DMAC) 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the DMA controller...
  • Page 343CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series 4. Registers This section explains registers of the DMA controller (DMAC)....
  • Page 344CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series Registers Address Register function +0 +1 +2 +3 0x0C5C DDAR5 DMA...
  • Page 345CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series Registers Address Register function +0 +1 +2 +3 DMA channel status...
  • Page 346CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series 4.1. DMA Control Register: DMACR (DMA Control Register) This section explains...
  • Page 347CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series [bit31] DME (DMA Enable) : DMA operation enabled This bit controls...
  • Page 348CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series 4.2. DMA Channel Control Register 0 to 15: DCCR0 to 15...
  • Page 349CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series [bit31] CE (Channel Enable) : Channel operation enabled This bit controls...
  • Page 350CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series [bit24] NIE (Normal completion Interrupt Enable) : Normal completion interrupt enabled...
  • Page 351CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series [bit14] SAR (Source Address Reload) : Transfer source address reload This...
  • Page 352CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series [bit9, bit8] DAC (Destination Address Count) : Transfer destination address count...
  • Page 353CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series [bit3 to bit0] BLK (Block Size) : Block size These bits...
  • Page 354CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series 4.3. DMA Channel Status Register 0 to 15 : DCSR0 to...
  • Page 355CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series When having allowed the abnormal completion interrupt (DCCRn:AIE), writing "0" to...
  • Page 356CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series 4.4. DMA Transfer Count Register 0 to 15 : DTCR0 to...
  • Page 357CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series 4.5. DMA Transfer Source Register 0 to 15 : DSAR0 to...
  • Page 358CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series 4.6. DMA Transfer Destination Register 0 to 15 : DDAR0 to...
  • Page 359CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series 4.7. DMA Transfer Suppression NMI Flag Register : DNMIR (DMA-halt by...
  • Page 360CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series 4.8. DMA Transfer Suppression Level Register : DILVR (DMA-halt by Interrupt...
  • Page 361CHAPTER 8: DMA CONTROLLER (DMAC) 4. Registers MB91520 Series LVL[4:0] DMA suppression control Suppresses the DMA transfer when a peripheral...
  • Page 362CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series 5. Operation This section explains the operation of the DMA controller...
  • Page 363CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series 5.1. Configuration This section explains the configuration for DMAC operation. The...
  • Page 364CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series 5.1.1. Common Items for All Channels The common Items for all...
  • Page 365CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series 5.1.2. Separate Items for Each Channel This section explains the separate...
  • Page 366CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series  Transfer Source Address and the Transfer Destination Address Setting Set...
  • Page 367CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series  Setting the ST Bit (Transfer source type) and DT Bit...
  • Page 368CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series  Transfer Count Reload Setting Using the DCCRn:TCR, set the reload...
  • Page 369CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series 5.1.3. Operations This section explains DMAC operations. This section explains the...
  • Page 370CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series • Block Transfer Mode 1-time transfer request causes the 1 block...
  • Page 371CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series • Burst transfer mode 1-time transfer request causes the continuous data...
  • Page 372CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series  Transfer request The transfer request has a request by software...
  • Page 373CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series Table 5-2 Relationship between Transfer Request Detection Conditions and Transfer Mode...
  • Page 374CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series Figure 5-4 Data Transfer Example 1 If Channel Priority Is Fixed...
  • Page 375CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series Figure 5-6 Data Transfer Example If Channel Priority Is Set by...
  • Page 376CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series Table 5-4 Updating of Transfer Source Address and Transfer Destination Address...
  • Page 377CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series  Reloading of transfer address The DMAC can reload the transfer...
  • Page 378CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series  Reloading of transfer count If the reloading of the transfer...
  • Page 379CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series (A) Multi-function serial interface If a PE, FRE, or ORE flag...
  • Page 380CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series ⋅ Transfer size : DCCRn:TS = 11 ⋅ Demand transfer mode...
  • Page 381CHAPTER 8: DMA CONTROLLER (DMAC) 5. Operation MB91520 Series When the interrupt request is cleared and the interrupt level drops...
  • Page 382CHAPTER 8: DMA CONTROLLER (DMAC) 6. DMA Usage Examples MB91520 Series 6. DMA Usage Examples DMA usage examples are shown....
  • Page 383CHAPTER 8: DMA CONTROLLER (DMAC) 6. DMA Usage Examples MB91520 Series This is a communication example via the multi-function serial...
  • Page 384CHAPTER 8: DMA CONTROLLER (DMAC) 6. DMA Usage Examples MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 346 CHAPTER : DMA CONTROLLER...
  • Page 385: CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTSCHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 1. Overview CHAPTER : GENERATION AND CLEARING OF DMA...
  • Page 386CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 1. Overview 1. Overview This section explains the overview...
  • Page 387CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 2. Features 2. Features This section explains features of...
  • Page 388CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 2. Features 2.1. Transfer Request Generation Setting The transfer...
  • Page 389CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 2. Features 2.2. Interrupt Clearing Setting The interrupt clearing...
  • Page 390CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 3. Configuration 3. Configuration This section explains the configuration...
  • Page 391CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4. Registers This section explains registers of...
  • Page 392CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers Addres Registers Register function s +0 +1...
  • Page 393CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.1. DMA Request Clear Register 0 :...
  • Page 394CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.2. DMA Request Clear Register 1 :...
  • Page 395CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.3. DMA Request Clear Register 2 :...
  • Page 396CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.4. DMA Request Clear Register 3 :...
  • Page 397CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.5. DMA Request Clear Register 5 :...
  • Page 398CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.6. DMA Request Clear Register 6 :...
  • Page 399CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.7. DMA Request Clear Register 7 :...
  • Page 400CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.8. DMA Request Clear Register 8 :...
  • Page 401CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.9. DMA Request Clear Register 9 :...
  • Page 402CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.10. DMA Request Clear Register 10 :...
  • Page 403CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.11. DMA Request Clear Register 11 :...
  • Page 404CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.12. DMA Request Clear Register 13 :...
  • Page 405CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.13. DMA Request Clear Register 14 :...
  • Page 406CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.14. DMA Request Clear Register 15 :...
  • Page 407CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.15. DMA Request Clear Register 16 :...
  • Page 408CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.16. DMA Request Clear Register 17 :...
  • Page 409CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.17. DMA Request Clear Register 18 :...
  • Page 410CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.18. DMA Request Clear Register 19 :...
  • Page 411CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.19. DMA Request Clear Register 20 :...
  • Page 412CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.20. DMA Request Clear Register 21 :...
  • Page 413CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.21. DMA Request Clear Register 22 :...
  • Page 414CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.22. DMA Request Clear Register 23 :...
  • Page 415CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.23. DMA Request Clear Register 24 :...
  • Page 416CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.24. DMA Request Clear Register 25 :...
  • Page 417CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers AD_SEL[4:0] Clear target 11010 A/D converter ch.26...
  • Page 418CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.25. DMA Request Clear Register 26 :...
  • Page 419CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.26. DMA Request Clear Register 27 :...
  • Page 420CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers 4.27. IO Transfer Request Setting Register 0...
  • Page 421CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 4. Registers Note: You cannot configure setting that causes...
  • Page 422CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 5. Operation 5. Operation This section explains the operation...
  • Page 423CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 5. Operation 5.1. Configuration The configuration of the operation...
  • Page 424CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS MB91520 Series 5. Operation 5.2. Notes The notes is shown. ⋅...
  • Page 425: CHAPTER 10: FIXEDVECTOR FUNCTIONCHAPTER 10: FIXEDVECTOR FUNCTION 1. Overview MB91520 Series CHAPTER : FIXEDVECTOR FUNCTION This chapter explains the FixedVector function. 1. Overview...
  • Page 426CHAPTER 10: FIXEDVECTOR FUNCTION 1. Overview MB91520 Series 1. Overview This section explains the overview of the FixedVector function. The...
  • Page 427CHAPTER 10: FIXEDVECTOR FUNCTION 2. Features MB91520 Series 2. Features This section explains the features of the FixedVector function. ⋅...
  • Page 428CHAPTER 10: FIXEDVECTOR FUNCTION 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the FixedVector function. See...
  • Page 429CHAPTER 10: FIXEDVECTOR FUNCTION 4. Registers MB91520 Series 4. Registers This section explains the registers of the FixedVector function. None....
  • Page 430CHAPTER 10: FIXEDVECTOR FUNCTION 5. Operation MB91520 Series 5. Operation This section explains the operation of the FixedVector function. 5.1....
  • Page 431CHAPTER 10: FIXEDVECTOR FUNCTION 5. Operation MB91520 Series 5.1. Operation After Reset Released The operation after reset released is shown...
  • Page 432CHAPTER 10: FIXEDVECTOR FUNCTION 5. Operation MB91520 Series 5.2. Usage The usage is shown below. After the reset is released,...
  • Page 433CHAPTER 10: FIXEDVECTOR FUNCTION 6. Notes MB91520 Series 6. Notes This section explains the notes of the FixedVector function. During...
  • Page 434CHAPTER 10: FIXEDVECTOR FUNCTION 6. Notes MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 396 CHAPTER : FIXEDVECTOR FUNCTION FUJITSU SEMICONDUCTOR CONFIDENTIAL...
  • Page 435: CHAPTER 11: I/O PORTSCHAPTER 11: I/O PORTS 1. Overview MB91520 Series CHAPTER : I/O PORTS This chapter explains the I/O ports. 1. Overview...
  • Page 436CHAPTER 11: I/O PORTS 1. Overview MB91520 Series 1. Overview This section explains the overview of the I/O ports. This...
  • Page 437CHAPTER 11: I/O PORTS 2. Features MB91520 Series 2. Features This section explains features of the I/O ports.  I/O...
  • Page 438CHAPTER 11: I/O PORTS 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the I/O ports. No...
  • Page 439CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4. Registers This section explains registers of the I/O ports. Registers Address...
  • Page 440CHAPTER 11: I/O PORTS 4. Registers MB91520 Series Registers Address Register function +0 +1 +2 +3 0x0E70 Reserved Reserved Reserved...
  • Page 441CHAPTER 11: I/O PORTS 4. Registers MB91520 Series Registers Address Register function +0 +1 +2 +3 0x0F20 Reserved Reserved Reserved...
  • Page 442CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.1. Port Data Register 00 to 19 : PDR00 to 19 (Port...
  • Page 443CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.2. Data Direction Register 00 to 19 : DDR00 to 19 (Data...
  • Page 444CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.3. Port Function Register 00 to 19 : PFR00 to 19 (Port...
  • Page 445CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.4. Input Data Direct Register 00 to 19 : PDDR00 to 19...
  • Page 446CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.5. Port Pull-up/down Enable Register 00 to 19 : PPER00 to 19...
  • Page 447CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6. Extended Port Function Register 00 to 88 : EPFR00 to 88...
  • Page 448 CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.1. Extended Port Function Register 00, 01, 56 : EPFR00, EPFR01, EPFR56...
  • Page 449CHAPTER 11: I/O PORTS 4. Registers MB91520 Series ICUnE[1:0] Operation (n=0 to 3) 00 Input from the ICUn_0 pin 01...
  • Page 450CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.2. Extended Port Function Register 02 to 05, 57 to 60 :...
  • Page 451CHAPTER 11: I/O PORTS 4. Registers MB91520 Series  EPFR57 : Address 0E99H (Access : Byte, Half-word, Word) bit7 bit6...
  • Page 452CHAPTER 11: I/O PORTS 4. Registers MB91520 Series TOTnE[2:0] Operation (n=1) 000 No output xx1 Output from the TOTn_0 pin...
  • Page 453CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.3. Extended Port Function Register 06 to 09, 33 to 36, 61...
  • Page 454CHAPTER 11: I/O PORTS 4. Registers MB91520 Series  EPFR08 : Address 0E68H (Access : Byte, Half-word, Word) bit7 bit6...
  • Page 455CHAPTER 11: I/O PORTS 4. Registers MB91520 Series  EPFR62 : Address 0E9EH (Access: Byte, Half-word, Word) bit7 bit6 bit5...
  • Page 456CHAPTER 11: I/O PORTS 4. Registers MB91520 Series SCK0, 1, 10 pin selection SCKnE[1:0] (n= 0, 1, 10) Operation 00...
  • Page 457CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.4. Extended Port Function Register 10 to 15, 45, 71 to 78...
  • Page 458 CHAPTER 11: I/O PORTS 4. Registers MB91520 Series  EPFR14 : Address 0E6EH (Access: Byte, Half-word, Word) bit7 bit6 bit5...
  • Page 459 CHAPTER 11: I/O PORTS 4. Registers MB91520 Series  EPFR72 : Address 01C0H (Access : Byte, Half-word, Word) bit7 bit6...
  • Page 460 CHAPTER 11: I/O PORTS 4. Registers MB91520 Series  EPFR76 : Address 01C4H (Access : Byte, Half-word, Word) bit7 bit6...
  • Page 461CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.5. Extended Port Function Register 79, 80 : EPFR79, 80 The bit...
  • Page 462CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.6. Extended Port Function Register 86 : EPFR86 The bit configuration of...
  • Page 463CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.7. Extended Port Function Register 26 : EPFR26 The bit configuration of...
  • Page 464CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.8. Extended Port Function Register 27 : EPFR27 The bit configuration of...
  • Page 465CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.9. Extended Port Function Register 28 : EPFR28 The bit configuration of...
  • Page 466 CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.10. Extended Port Function Register 29, 81, 82 : EPFR29, 81, 82...
  • Page 467CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.11. Extended Port Function Register 83 : EPFR83 The bit configuration of...
  • Page 468CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.12. Extended Port Function Register 42 : EPFR42 The bit configuration of...
  • Page 469CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.13. Extended Port Function Register 43, 44 : EPFR43, 44 The bit...
  • Page 470CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.14. Extended Port Function Register 48 to 51 : EPFR48 to 51...
  • Page 471CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.15. Extended Port Function Register 65 to 70 : EPFR65 to 70...
  • Page 472 CHAPTER 11: I/O PORTS 4. Registers MB91520 Series  EPFR68 : Address 01BCH (Access: Byte, Half-word, Word) bit7 bit6 bit5...
  • Page 473CHAPTER 11: I/O PORTS 4. Registers MB91520 Series SCSOnE (n=1,3,40 to Operation 43, 10) 00 Input from the SCSn_0 pin,...
  • Page 474CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.16. Extended Port Function Register 84, 85 : EPFR84, 85 The bit...
  • Page 475CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.17. Extended Port Function Register 87 : EPFR87 The bit configuration of...
  • Page 476CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.6.18. Extended Port Function Register 88 : EPFR88 The bit configuration of...
  • Page 477CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.7. Port Input Enable Register: PORTEN (PORT ENable register) The bit configuration...
  • Page 478CHAPTER 11: I/O PORTS 4. Registers MB91520 Series 4.8. KEY CoDe Register : KEYCDR The bit configuration of key code...
  • Page 479CHAPTER 11: I/O PORTS 4. Registers MB91520 Series [bit12 to bit0] RADR[12:0]: Port address Set the lower 13 bits of...
  • Page 480CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5. Operation This section explains operations of I/O ports. 5.1. Pin I/O...
  • Page 481CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.1. Pin I/O Assignment The pin I/O assignment is shown below. Pin...
  • Page 482CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.1.1. Peripheral I/O (bidirectional) Pin Assignment The peripheral I/O (bidirectional) pin assignment...
  • Page 483CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.1.2. Peripheral Input Assignment The peripheral input assignment is shown below. ...
  • Page 484CHAPTER 11: I/O PORTS 5. Operation MB91520 Series Note: As shown in the figure above, if the pin is set...
  • Page 485CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.1.3. Peripheral Output Assignment The peripheral output assignment is shown below. The...
  • Page 486CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.1.4. External Bus Assignment The external bus assignment is shown below. ...
  • Page 487CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.1.5. Port Function (Input) Assignment The port function (input) assignment is shown...
  • Page 488CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.1.6. Port Function (Output) Assignment The port function (Output) assignment is shown...
  • Page 489CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.1.7. AD Converter Input Assignment The AD converter input assignment is shown...
  • Page 490CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.1.8. DA converter output assignment The DA converter output assignment is shown...
  • Page 491CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.2. EPFR setting priority The EPFR setting priority is explained below. If...
  • Page 492CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.3. Notes on Input I/O Relocation Setting Notes on input I/O relocation...
  • Page 493CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.4. Noise Filter The noise filter is shown. If an external pin...
  • Page 494CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.5. Input blocked by GPORTEN The input blocked function by GPORTEN is...
  • Page 495CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.6. Notes on Pins with the AD Converter Function Notes on pins...
  • Page 496CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.7. Setting when Using the Base Timer TIOA1 Pin Setting when using...
  • Page 497CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.8. Key Code Register Function Settings Setting when using the Key Code...
  • Page 498 CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.9. Operation at Wake Up from Power Shutdown The operation at wake...
  • Page 499CHAPTER 11: I/O PORTS 5. Operation MB91520 Series 5.10. Notes on switching the I/O port function Notes on switching the...
  • Page 500CHAPTER 11: I/O PORTS 5. Operation MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 462 CHAPTER : I/O PORTS FUJITSU SEMICONDUCTOR CONFIDENTIAL...
  • Page 501: CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER)CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER) MB91520 Series 1. Overview CHAPTER : INTERRUPT CONTROL (INTERRUPT CONTROLLER) This chapter explains the...
  • Page 502CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER) MB91520 Series 1. Overview 1. Overview This section explains overview the of the interrupt...
  • Page 503CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER) MB91520 Series 2. Features 2. Features This section explains features of the interrupt control...
  • Page 504CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER) MB91520 Series 3. Configuration 3. Configuration This section explains the configuration of the interrupt...
  • Page 505CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER) MB91520 Series 4. Registers 4. Registers This section explains the registers of the interrupt...
  • Page 506CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER) MB91520 Series 4. Registers 4.1. Interrupt Control Registers 00 to 47 : ICR00 to...
  • Page 507CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER) MB91520 Series 5. Operation 5. Operation This section explains the operation of the interrupt...
  • Page 508CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER) MB91520 Series 5. Operation 5.1. Setup This section explains the setup of the interrupt...
  • Page 509CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER) MB91520 Series 5. Operation 5.2. Starting This section explains the starting of the interrupt...
  • Page 510CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER) MB91520 Series 5. Operation 5.3. Determining Priorities The determining priorities is shown below. This...
  • Page 511CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER) MB91520 Series 5. Operation 5.4. Recovering From Stop Mode The recovering from stop mode...
  • Page 512CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER) MB91520 Series 5. Operation 5.5. Recovering From Standby Mode (Power shutdown) The recovering from...
  • Page 513: CHAPTER 13: EXTERNAL INTERRUPT INPUTCHAPTER 13: EXTERNAL INTERRUPT INPUT 1. Overview MB91520 Series CHAPTER : EXTERNAL INTERRUPT INPUT This chapter explains the external interrupt...
  • Page 514CHAPTER 13: EXTERNAL INTERRUPT INPUT 1. Overview MB91520 Series 1. Overview This section explains the overview of the external interrupt...
  • Page 515CHAPTER 13: EXTERNAL INTERRUPT INPUT 2. Features MB91520 Series 2. Features This section explains features of the external interrupt input....
  • Page 516CHAPTER 13: EXTERNAL INTERRUPT INPUT 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the external interrupt...
  • Page 517CHAPTER 13: EXTERNAL INTERRUPT INPUT 4. Registers MB91520 Series 4. Registers This section explains registers of the external interrupt input....
  • Page 518CHAPTER 13: EXTERNAL INTERRUPT INPUT 4. Registers MB91520 Series 4.1. External Interrupt Factor Register 0/1 : EIRR0/EIRR1 (External Interrupt Request...
  • Page 519CHAPTER 13: EXTERNAL INTERRUPT INPUT 4. Registers MB91520 Series 4.2. External Interrupt Enable Register 0/1 : ENIR0/ENIR1 (ENable Interrupt request...
  • Page 520CHAPTER 13: EXTERNAL INTERRUPT INPUT 4. Registers MB91520 Series 4.3. External Interrupt Request Level Register 0/1 : ELVR0/ELVR1 (External interrupt...
  • Page 521CHAPTER 13: EXTERNAL INTERRUPT INPUT 5. Operation MB91520 Series 5. Operation This section explains the operation of the external interrupt...
  • Page 522CHAPTER 13: EXTERNAL INTERRUPT INPUT 5. Operation MB91520 Series (1) Disable the corresponding bit for the enable register. (2) Set...
  • Page 523CHAPTER 13: EXTERNAL INTERRUPT INPUT 6. Setting MB91520 Series 6. Setting This section explains settings of the external interrupt input....
  • Page 524CHAPTER 13: EXTERNAL INTERRUPT INPUT 7. Q&A MB91520 Series 7. Q&A This section explains Q&A of the external interrupt input....
  • Page 525CHAPTER 13: EXTERNAL INTERRUPT INPUT 8. Notes MB91520 Series 8. Notes This section explains the notes of the external interrupt...
  • Page 526CHAPTER 13: EXTERNAL INTERRUPT INPUT 8. Notes MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 488 CHAPTER : EXTERNAL INTERRUPT INPUT FUJITSU...
  • Page 527: CHAPTER 14: NMI INPUTCHAPTER 14: NMI INPUT 1. Overview MB91520 Series CHAPTER : NMI INPUT This chapter explains the NMI input. 1. Overview...
  • Page 528CHAPTER 14: NMI INPUT 1. Overview MB91520 Series 1. Overview This section explains the overview of the NMI input. NMI...
  • Page 529CHAPTER 14: NMI INPUT 2. Features MB91520 Series 2. Features This section explains features of the NMI input Can be...
  • Page 530CHAPTER 14: NMI INPUT 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the NMI input. Figure...
  • Page 531CHAPTER 14: NMI INPUT 4. Register MB91520 Series 4. Register This section explains the register of the NMI input. This...
  • Page 532CHAPTER 14: NMI INPUT 5. Operation MB91520 Series 5. Operation This section explains the operation of the NMI input. ...
  • Page 533CHAPTER 14: NMI INPUT 6. Usage Example MB91520 Series 6. Usage Example This section explains a usage example of the...
  • Page 534CHAPTER 14: NMI INPUT 6. Usage Example MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 496 CHAPTER : NMI INPUT FUJITSU SEMICONDUCTOR...
  • Page 535: CHAPTER 15: DELAY INTERRUPTCHAPTER 15: DELAY INTERRUPT 1. Overview MB91520 Series CHAPTER : DELAY INTERRUPT This chapter explains the delay interrupt. 1. Overview...
  • Page 536CHAPTER 15: DELAY INTERRUPT 1. Overview MB91520 Series 1. Overview This section explains the overview of the delay interrupt. The...
  • Page 537CHAPTER 15: DELAY INTERRUPT 2. Features MB91520 Series 2. Features This section explains features of the delay interrupt. The delay...
  • Page 538CHAPTER 15: DELAY INTERRUPT 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the delay interrupt. Figure...
  • Page 539CHAPTER 15: DELAY INTERRUPT 4. Registers MB91520 Series 4. Registers This section explains registers of the delay interrupt. Registers Address...
  • Page 540CHAPTER 15: DELAY INTERRUPT 5. Operation MB91520 Series 5. Operation This section explains the operation description of the delay interrupt....
  • Page 541CHAPTER 15: DELAY INTERRUPT 6. Restrictions MB91520 Series 6. Restrictions This section explains restrictions of the delay interrupt. Do not...
  • Page 542CHAPTER 15: DELAY INTERRUPT 6. Restrictions MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 504 CHAPTER : DELAY INTERRUPT FUJITSU SEMICONDUCTOR CONFIDENTIAL...
  • Page 543: CHAPTER 16: INTERRUPT REQUEST BATCH READCHAPTER 16: INTERRUPT REQUEST BATCH READ 1. Overview MB91520 Series CHAPTER : INTERRUPT REQUEST BATCH READ This chapter explains the...
  • Page 544CHAPTER 16: INTERRUPT REQUEST BATCH READ 1. Overview MB91520 Series 1. Overview This section explains the overview of the interrupt...
  • Page 545CHAPTER 16: INTERRUPT REQUEST BATCH READ 2. Features MB91520 Series 2. Features This section shows features of the interrupt request...
  • Page 546CHAPTER 16: INTERRUPT REQUEST BATCH READ 3. Configuration MB91520 Series 3. Configuration This section shows the configuration of the interrupt...
  • Page 547CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4. Registers This section explains the registers of the interrupt...
  • Page 548CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series Registers Address Register function +0 +1 +2 +3 Interrupt request...
  • Page 549CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.1. Interrupt Request Batch Read Register 0 upper-order : IRPR0H...
  • Page 550CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.2. Interrupt Request Batch Read Register 0 lower-order : IRPR0L...
  • Page 551CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.3. Interrupt Request Batch Read Register 1 upper-order : IRPR1H...
  • Page 552CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.4. Interrupt Request Batch Read Register 1 lower-order : IRPR1L...
  • Page 553CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.5. Interrupt Request Batch Read Register 3 upper-order : IRPR3H...
  • Page 554CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.6. Interrupt Request Batch Read Register 3 lower-order : IRPR3L...
  • Page 555CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.7. Interrupt Request Batch Read Register 4 upper-order : IRPR4H...
  • Page 556CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.8. Interrupt Request Batch Read Register 4 lower-order : IRPR4L...
  • Page 557CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.9. Interrupt Request Batch Read Register 5 upper-order : IRPR5H...
  • Page 558CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.10. Interrupt Request Batch Read Register 5 lower-order : IRPR5L...
  • Page 559CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.11. Interrupt Request Batch Read Register 6 upper-order : IRPR6H...
  • Page 560CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.12. Interrupt Request Batch Read Register 6 lower-order : IRPR6L...
  • Page 561CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.13. Interrupt Request Batch Read Register 7 upper-order : IRPR7H...
  • Page 562CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.14. Interrupt Request Batch Read Register 7 lower-order : IRPR7L...
  • Page 563CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.15. Interrupt Request Batch Read Register 8 upper-order IRPR8H (Interrupt...
  • Page 564CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.16. Interrupt Request Batch Read Register 8 lower-order : IRPR8L...
  • Page 565CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.17. Interrupt Request Batch Read Register 9 upper-order : IRPR9H...
  • Page 566CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.18. Interrupt Request Batch Read Register 9 lower-order : IRPR9L...
  • Page 567CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.19. Interrupt Request Batch Read Register 10 upper-order : IRPR10H...
  • Page 568CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.20. Interrupt Request Batch Read Register 10 lower-order : IRPR10L...
  • Page 569CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.21. Interrupt Request Batch Read Register 11 upper-order : IRPR11H...
  • Page 570CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.22. Interrupt Request Batch Read Register 11 lower-order : IRPR11L...
  • Page 571CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.23. Interrupt Request Batch Read Register 12 upper-order : IRPR12H...
  • Page 572CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.24. Interrupt Request Batch Read Register 12 lower-order : IRPR12L...
  • Page 573CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.25. Interrupt Request Batch Read Register 13 upper-order : IRPR13H...
  • Page 574CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.26. Interrupt Request Batch Read Register 13 lower-order : IRPR13L...
  • Page 575CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.27. Interrupt Request Batch Read Register 14 upper-order : IRPR14H...
  • Page 576CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.28. Interrupt Request Batch Read Register 14 lower-order : IRPR14L...
  • Page 577CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.29. Interrupt Request Batch Read Register 15 upper-order : IRPR15H...
  • Page 578CHAPTER 16: INTERRUPT REQUEST BATCH READ 4. Registers MB91520 Series 4.30. Interrupt Request Batch Read Register 15 lower-order : IRPR15L...
  • Page 579CHAPTER 16: INTERRUPT REQUEST BATCH READ 5. Operation MB91520 Series 5. Operation This section explains the operation of the interrupt...
  • Page 580CHAPTER 16: INTERRUPT REQUEST BATCH READ 5. Operation MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 542 CHAPTER : INTERRUPT REQUEST BATCH...
  • Page 581: CHAPTER 17: PPGCHAPTER 17: PPG 1. Overview MB91520 Series CHAPTER : PPG This chapter explains the PPG. 1. Overview 2. Features 3....
  • Page 582CHAPTER 17: PPG 1. Overview MB91520 Series 1. Overview This section explains the overview of the PPG. The programmable pulse...
  • Page 583CHAPTER 17: PPG 2. Features MB91520 Series 2. Features This section explains features of the PPG.  Clamp output ...
  • Page 584CHAPTER 17: PPG 2. Features MB91520 Series ⋅ One-shot Waveform (rectangular wave) Normal Wave Form Normal L H Polarity Inverted...
  • Page 585CHAPTER 17: PPG 2. Features MB91520 Series ⋅ High/Low format Waveform The cycle of the High format and the Low...
  • Page 586CHAPTER 17: PPG 2. Features MB91520 Series  Interrupt factors ⋅ One of the following six interrupts is selected: ⋅...
  • Page 587CHAPTER 17: PPG 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the PPG. Figure 3-1 Configuration...
  • Page 588CHAPTER 17: PPG 4. Registers MB91520 Series 4. Registers This section explains registers of the PPG. The registers of PPG...
  • Page 589CHAPTER 17: PPG 4. Registers MB91520 Series Address +0 +1 +2 +3 PPG (ch.3) communication mode data setting 0x1AAC Reserved...
  • Page 590CHAPTER 17: PPG 4. Registers MB91520 Series Address +0 +1 +2 +3 0x1B40 PPG (ch.13) control status register (PCN13) PPG...
  • Page 591CHAPTER 17: PPG 4. Registers MB91520 Series Address +0 +1 +2 +3 PPG (ch.22) Start Delay value setting register 0x1BD8...
  • Page 592CHAPTER 17: PPG 4. Registers MB91520 Series Address +0 +1 +2 +3 PPG (ch.31) Timing Point Capture value setting 0x1C6C...
  • Page 593CHAPTER 17: PPG 4. Registers MB91520 Series Address +0 +1 +2 +3 0x1D00 PPG (ch.41) control status register (PCN41) PPG...
  • Page 594CHAPTER 17: PPG 4. Registers MB91520 Series  List of GATE Function Control Registers Map Address +0 +1 +2 +3...
  • Page 595CHAPTER 17: PPG 4. Registers MB91520 Series 4.1. PPG Control Status Register : PCN0 to PCN 47 The bit configuration...
  • Page 596CHAPTER 17: PPG 4. Registers MB91520 Series [bit13] MDSE : Mode selection bit MDSE Explanation 0 PWM operation 1 One-shot...
  • Page 597CHAPTER 17: PPG 4. Registers MB91520 Series [bit8] OWFS : PPG output waveform selection bit OWFS Explanation 0 Normal Wave...
  • Page 598CHAPTER 17: PPG 4. Registers MB91520 Series [bit3, bit2] IRS1, IRS0 : Interrupt factor selection bits IRS1, IRS0 Explanation STGR=0:...
  • Page 599CHAPTER 17: PPG 4. Registers MB91520 Series 4.2. PPG Cycle Setting Register : PCSR0 to PCSR47 The bit configuration of...
  • Page 600CHAPTER 17: PPG 4. Registers MB91520 Series 4.3. PPG Duty Setting Register : PDUT0 to PDUT47 The bit configuration of...
  • Page 601CHAPTER 17: PPG 4. Registers MB91520 Series 4.4. PPG Timer Register : PTMR0 to PTMR47 The bit configuration of the...
  • Page 602CHAPTER 17: PPG 4. Registers MB91520 Series 4.5. PPG Control Status Register2 : PCN200 to PCN247 The bit configuration of...
  • Page 603CHAPTER 17: PPG 4. Registers MB91520 Series [bit10] CMD : PPG communication mode enable bit CMD Explanation 0 PPG communication...
  • Page 604CHAPTER 17: PPG 4. Registers MB91520 Series 4.6. Start Delay Value Setting Register : PSDR0 to PSDR47 The bit configuration...
  • Page 605CHAPTER 17: PPG 4. Registers MB91520 Series 4.7. Timing Point Capture Value Setting Register : PTPC0 to PTPC47 The bit...
  • Page 606CHAPTER 17: PPG 4. Registers MB91520 Series 4.8. PPG Communication Mode High Format Cycle Setting Register : PHCSR0 to PHCSR3...
  • Page 607CHAPTER 17: PPG 4. Registers MB91520 Series 4.9. PPG Communication Mode Low Format Cycle Setting Register : PLCSR0 to PLCSR3...
  • Page 608CHAPTER 17: PPG 4. Registers MB91520 Series 4.10. PPG Communication Mode High Format Duty Setting Register : PHDUT0 to PHDUT3...
  • Page 609CHAPTER 17: PPG 4. Registers MB91520 Series 4.11. PPG Communication Mode Low Format Duty Setting Register : PLDUT0 to PLDUT3...
  • Page 610CHAPTER 17: PPG 4. Registers MB91520 Series 4.12. PPG Communication Mode Data Setting Register : PCMDDT0 to PCMDDT3 The bit...
  • Page 611CHAPTER 17: PPG 4. Registers MB91520 Series 4.13. PPG Communication Mode Data Bit Length Setting Register : PCMDWD0 to PCMDWD3...
  • Page 612CHAPTER 17: PPG 4. Registers MB91520 Series 4.14. GATE Function Control Register : GATEC0, GATEC2, GATEC4 The bit configuration of...
  • Page 613CHAPTER 17: PPG 4. Registers MB91520 Series 4.15. General-purpose Trigger Selection Register : GTRS0 to GTRS23 The bit configuration of...
  • Page 614CHAPTER 17: PPG 4. Registers MB91520 Series [bit14 to bit8] / [bit6 to bit0] TSELii [6:0]: Activation trigger selection bits...
  • Page 615CHAPTER 17: PPG 4. Registers MB91520 Series TSELii [6:0] Activation trigger selection 0 1 0 0 1 1 1 Internal...
  • Page 616CHAPTER 17: PPG 4. Registers MB91520 Series 4.16. General-purpose Trigger Setting Register : GTREN0 to GTREN2 The bit configuration of...
  • Page 617CHAPTER 17: PPG 4. Registers MB91520 Series  General-purpose trigger setting register 2 (GTREN2): Address 1A3CH (Access: Half-word, Word) bit15...
  • Page 618CHAPTER 17: PPG 5. Operation MB91520 Series 5. Operation This section explains the operation of the PPG. MN705-00010-1v0-E FUJITSU SEMICONDUCTOR...
  • Page 619CHAPTER 17: PPG 5. Operation MB91520 Series 5.1. PWM Operation (Normal Wave Form) The PWM operation (Normal Wave Form) is...
  • Page 620CHAPTER 17: PPG 5. Operation MB91520 Series Setting and operation procedure: (1) Writing of PCSR (cycle value) (2) Writing of...
  • Page 621CHAPTER 17: PPG 5. Operation MB91520 Series 5.2. PWM Operation (Center Aligned Wave Form Selected) The PWM operation (Center Aligned...
  • Page 622CHAPTER 17: PPG 5. Operation MB91520 Series Setting and operation procedure: (1) Writing of PCSR (cycle value) (2) Writing of...
  • Page 623CHAPTER 17: PPG 5. Operation MB91520 Series 5.3. One-shot Operation (Normal Wave Form Selected) The One-shot operation (Normal Wave Form...
  • Page 624CHAPTER 17: PPG 5. Operation MB91520 Series Setting and operation procedure: (1) Writing of PCSR (cycle value) (2) Writing of...
  • Page 625CHAPTER 17: PPG 5. Operation MB91520 Series 5.4. One-shot Operation (Center Aligned Wave Form Selected) The One-shot operation (Center Aligned...
  • Page 626CHAPTER 17: PPG 5. Operation MB91520 Series Setting and operation procedure: (1) Writing of PCSR (cycle value) (2) Writing of...
  • Page 627CHAPTER 17: PPG 5. Operation MB91520 Series 5.5. Restart Operation The restart operation is explained. Restart operation is as follows:...
  • Page 628CHAPTER 17: PPG 5. Operation MB91520 Series 5.6. GATE Operation The GATE operation is explained. PPG can be activated/stopped by...
  • Page 629CHAPTER 17: PPG 5. Operation MB91520 Series 5.7. Start Delay Mode Operation (PWM Normal Wave Form Selected) The Start Delay...
  • Page 630CHAPTER 17: PPG 5. Operation MB91520 Series Setting and operation procedure: (1) Writing of PSDR (Delay value) (2) Writing of...
  • Page 631CHAPTER 17: PPG 5. Operation MB91520 Series 5.8. Timing Point Capture Mode Operation (PWM Normal Wave Form Selected) The Timing...
  • Page 632CHAPTER 17: PPG 5. Operation MB91520 Series Setting and operation procedure: (1) Writing of PTPC (Timing Point Capture value) (2)...
  • Page 633CHAPTER 17: PPG 5. Operation MB91520 Series 5.9. PPG Communication Mode Operation The PPG communication mode operation is explained. In...
  • Page 634CHAPTER 17: PPG 5. Operation MB91520 Series 5.10. PPG Communication Activation The PPG communication activation is explained. The PPG communication...
  • Page 635CHAPTER 17: PPG 5. Operation MB91520 Series 5.11. PPG Communication Operation The PPG communication operation is explained. After it is...
  • Page 636CHAPTER 17: PPG 5. Operation MB91520 Series Setting and operation procedure: (1) Writing of PHCSR/PLCSR (High/Low format cycle values) (2)...
  • Page 637CHAPTER 17: PPG 5. Operation MB91520 Series  PPG Continuousness Communication Operation Figure 5-13 Example of PPG Communication Mode Operation...
  • Page 638CHAPTER 17: PPG 5. Operation MB91520 Series Setting and operation procedure: (1) Writing of PHCSR/PLCSR (High/Low format cycle values) (2)...
  • Page 639CHAPTER 17: PPG 5. Operation MB91520 Series 5.12. PPG Communication Forced Stop and Restart operation The PPG communication forced stop...
  • Page 640CHAPTER 17: PPG 5. Operation MB91520 Series Setting and operation procedure: (1) Writing of PHCSR/PLCSR (High/Low format cycle values) (2)...
  • Page 641CHAPTER 17: PPG 5. Operation MB91520 Series 5.13. PPG Output Pulse Polarity Selection The PPG output pulse polarity selection is...
  • Page 642CHAPTER 17: PPG 5. Operation MB91520 Series Setting and operation procedure: (1) Writing of PHCSR/PLCSR (High/Low format cycle values) (2)...
  • Page 643CHAPTER 17: PPG 5. Operation MB91520 Series 5.14. Interrupt The interrupt is explained. The interrupt request is generated for the...
  • Page 644CHAPTER 17: PPG 6. Notes MB91520 Series 6. Notes This section explains notes of the PPG. Note the following when...
  • Page 645CHAPTER 17: PPG 6. Notes MB91520 Series  Cycle Value (PCSR) and Duty (PDUT) Settings 7. When writing a cycle...
  • Page 646CHAPTER 17: PPG 6. Notes MB91520 Series  Start Delay Function 16. To activate the Start Delay mode, the timer...
  • Page 647CHAPTER 17: PPG 6. Notes MB91520 Series 27. In the PPG communication mode, the register that becomes valid or invalid...
  • Page 648CHAPTER 17: PPG 6. Notes MB91520 Series 39. Notes the following when rewriting the cycle value (PHCSR/PLCSR) and the duty...
  • Page 649: CHAPTER 18: WATCHDOG TIMERCHAPTER 18: WATCHDOG TIMER 1. Overview MB91520 Series CHAPTER : WATCHDOG TIMER This chapter explains the watchdog timer. 1. Overview...
  • Page 650CHAPTER 18: WATCHDOG TIMER 1. Overview MB91520 Series 1. Overview This section gives an overview of the watchdog timer. This...
  • Page 651CHAPTER 18: WATCHDOG TIMER 2. Features MB91520 Series 2. Features This section explains features of the watchdog timer. 2.1 Watchdog...
  • Page 652CHAPTER 18: WATCHDOG TIMER 2. Features MB91520 Series 2.1. Watchdog Timer 0 (Software Watchdog) This section explains features of the...
  • Page 653CHAPTER 18: WATCHDOG TIMER 2. Features MB91520 Series 2.2. Watchdog Timer 1 (Hardware Watchdog) This section explains features of the...
  • Page 654CHAPTER 18: WATCHDOG TIMER 3. Configuration MB91520 Series 3. Configuration This section shows the configuration of the watchdog timer. Figure...
  • Page 655CHAPTER 18: WATCHDOG TIMER 4. Registers MB91520 Series 4. Registers This section explains the registers of the watchdog timer. Table...
  • Page 656CHAPTER 18: WATCHDOG TIMER 4. Registers MB91520 Series 4.1. Watchdog Control Register 0 : WDTCR0 (WatchDog Timer Configuration Register 0)...
  • Page 657CHAPTER 18: WATCHDOG TIMER 4. Registers MB91520 Series WT[3:0] The Watchdog Timer 0 cycle 1001 PCLK × 218 cycles 1010...
  • Page 658CHAPTER 18: WATCHDOG TIMER 4. Registers MB91520 Series 4.2. Watchdog Timer 0 Clear Register : WDTCPR0 (WatchDog Timer Clear Pattern...
  • Page 659CHAPTER 18: WATCHDOG TIMER 4. Registers MB91520 Series 4.3. Watchdog Timer 0 Extended Configuration Register : WDTECR0 (Watchdog Timer Extended...
  • Page 660CHAPTER 18: WATCHDOG TIMER 4. Registers MB91520 Series WTLI[3:0] The Lower Limit of the Watchdog Timer 1011 PCLK × 219...
  • Page 661CHAPTER 18: WATCHDOG TIMER 4. Registers MB91520 Series 4.4. Watchdog Timer 1 Cycle information Register : WDTCR1 (WatchDog Timer Cycle...
  • Page 662CHAPTER 18: WATCHDOG TIMER 4. Registers MB91520 Series 4.5. Watchdog Timer 1 Clear Register : WDTCPR1 (WatchDog Timer Clear Pattern...
  • Page 663CHAPTER 18: WATCHDOG TIMER 5. Operation MB91520 Series 5. Operation This section explains operation of the watchdog timer. The following...
  • Page 664CHAPTER 18: WATCHDOG TIMER 5. Operation MB91520 Series 5.1. Software Watchdog Function This section explains the software watchdog function 5.1.1...
  • Page 665CHAPTER 18: WATCHDOG TIMER 5. Operation MB91520 Series 5.1.1. Settings This section explains settings of the software watchdog function. Before...
  • Page 666CHAPTER 18: WATCHDOG TIMER 5. Operation MB91520 Series 5.1.2. Activation This section explains activation of the software watchdog function. The...
  • Page 667CHAPTER 18: WATCHDOG TIMER 5. Operation MB91520 Series 5.1.3. Operation This section explains operation of the software watchdog function. The...
  • Page 668CHAPTER 18: WATCHDOG TIMER 5. Operation MB91520 Series 5.2. Hardware Watchdog Function This section explains operation of the hardware watchdog...
  • Page 669CHAPTER 18: WATCHDOG TIMER 5. Operation MB91520 Series 5.2.1. Settings This section explains settings of the hardware watchdog function. The...
  • Page 670CHAPTER 18: WATCHDOG TIMER 5. Operation MB91520 Series 5.2.2. Activation This section explains activation of the hardware watchdog function. The...
  • Page 671CHAPTER 18: WATCHDOG TIMER 5. Operation MB91520 Series 5.2.3. Operation This section explains operation of the hardware watchdog function. The...
  • Page 672CHAPTER 18: WATCHDOG TIMER 6. Usage Example MB91520 Series 6. Usage Example This section gives an example of how the...
  • Page 673: CHAPTER 19: BASE TIMERCHAPTER 19: BASE TIMER 1. Overview MB91520 Series CHAPTER : BASE TIMER This chapter explains the base timer. 1. Overview...
  • Page 674CHAPTER 19: BASE TIMER 1. Overview MB91520 Series 1. Overview This section explains the overview of the base timer. This...
  • Page 675CHAPTER 19: BASE TIMER 2. Features MB91520 Series 2. Features This section explains features of the base timer. This series...
  • Page 676CHAPTER 19: BASE TIMER 2. Features MB91520 Series 2.1. 16/32-bit Reload Timer This section explains the 16/32-bit reload timer of...
  • Page 677CHAPTER 19: BASE TIMER 2. Features MB91520 Series 2.2. 16-bit PWM Timer This section explains the 16-bit PWM timer of...
  • Page 678CHAPTER 19: BASE TIMER 2. Features MB91520 Series 2.3. 16/32-bit PWC Timer This section explains the overview of the 16/32-bit...
  • Page 679CHAPTER 19: BASE TIMER 2. Features MB91520 Series 2.4. 16-bit PPG Timer This section explains the 16-bit PPG timer of...
  • Page 680CHAPTER 19: BASE TIMER 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the base timer. Figure...
  • Page 681CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4. Registers This section explains registers of the base timer.  List...
  • Page 682CHAPTER 19: BASE TIMER 4. Registers MB91520 Series  Registers Map Table 4-2 Registers Map Registers Address Register function +0...
  • Page 683CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.1. Common Registers This section explains the common registers of the base...
  • Page 684CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.1.1. Timer Registers 0, 1 : BTxTMR (Base Timer 0/1 TiMer Register)...
  • Page 685CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.1.2. Timer Control Registers 0, 1 : BTxTMCR (Base Timer 0/1 TiMer...
  • Page 686CHAPTER 19: BASE TIMER 4. Registers MB91520 Series  BTxTMCR2 : Address Base_addr + 04H (Access: Byte) bit15 bit14 bit13...
  • Page 687CHAPTER 19: BASE TIMER 4. Registers MB91520 Series PMSK Description 0 Normal output 1 Fixed output If the fixed output...
  • Page 688CHAPTER 19: BASE TIMER 4. Registers MB91520 Series Select whether to run the 16/32-bit timer individually by each channel or...
  • Page 689CHAPTER 19: BASE TIMER 4. Registers MB91520 Series MDSE Description Reload mode: When the down counter underflows, the value of...
  • Page 690CHAPTER 19: BASE TIMER 4. Registers MB91520 Series [PPG] MDSE Description Reload mode: A sequence of "L"-level and "H"-level signals...
  • Page 691CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.1.3. I/O Selection Register : BTSEL01 (Base Timer SElect register ch.0 and...
  • Page 692CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.1.4. Simultaneous Software Activation Register : BTSSSR (Base Timer Software Synchronous Start...
  • Page 693CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.2. Registers for 16/32-bit Reload Timer This section explains registers for 16/32-bit...
  • Page 694CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.2.1. Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus...
  • Page 695CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.2.2. Cycle Setting Registers 0, 1 : BTxPCSR (Base Timer 0/1 Pulse...
  • Page 696CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.3. Registers for 16-bit PWM Timer This section explains registers for 16-bit...
  • Page 697CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.3.1. Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus...
  • Page 698CHAPTER 19: BASE TIMER 4. Registers MB91520 Series TGIR/DTIR/UDIR Read Write A trigger detection, duty match 0 This bit is...
  • Page 699CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.3.2. Cycle Setting Registers 0, 1 : BTxPCSR (Base Timer 0/1 Pulse...
  • Page 700CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.3.3. Duty Setting Registers 0, 1 : BTxPDUT (Base Timer 0/1 Pulse...
  • Page 701CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.4. Registers for 16-bit PPG Timer This section explains registers for 16-bit...
  • Page 702CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.4.1. Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus...
  • Page 703CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.4.2. L Width Setting Registers 0, 1 : BTxPRLL (Base Timer 0/1...
  • Page 704CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.4.3. H Width Setting Registers 0, 1 : BTxPRLH (Base Timer 0/1...
  • Page 705CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.5. 16/32-bit PWC Timer Register This section explains registers for 16/32-bit PWC...
  • Page 706CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.5.1. Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus...
  • Page 707CHAPTER 19: BASE TIMER 4. Registers MB91520 Series [bit2] EDIR (EnD Interrupt Register) : Measurement completion interrupt request flag bit...
  • Page 708CHAPTER 19: BASE TIMER 4. Registers MB91520 Series 4.5.2. Data Buffer Registers 0, 1 : BTxDTBF (Base Timer 0/1 DaTa...
  • Page 709CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5. Operation This section explains the operation of the base timer. 5.1....
  • Page 710CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.1. Selection of Timer Function This section explains selection of the timer...
  • Page 711CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.2. I/O Allocation This section explains I/O allocation. Set I/O of the...
  • Page 712CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Figure 5-1 Wiring Diagram of Each I/O Mode (1) Block diagram for...
  • Page 713CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Figure 5-2 Wiring Diagram of Each I/O Mode (2) Block diagram for...
  • Page 714CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.3. 32-bit Mode Operation This section explains the 32-bit mode operation. The...
  • Page 715CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.3.1. 32-bit Mode Function This section explains the 32-bit mode function. This...
  • Page 716CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.3.2. 32-bit Mode Setting This section explains the 32-bit mode setting. First,...
  • Page 717CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.3.3. 32-bit Mode Operation This section explains 32-bit mode operation. After setting...
  • Page 718CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.4. 16/32-bit Reload Timer Operation This section explains the 16/32-bit reload timer...
  • Page 719CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Figure 5-4 Block Diagram (32-bit Reload Timer Operation) ch.1 BT1PCSR 16 Load...
  • Page 720CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.4.1. Overview This section explains the overview of the 16/32-bit reload timer...
  • Page 721CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.4.2. Operation in Reload Mode This section explains the operation in reload...
  • Page 722CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Figure 5-5 and Figure 5-6 show the count start timing. Figure 5-5...
  • Page 723CHAPTER 19: BASE TIMER 5. Operation MB91520 Series  Output Waveform The waveform (TOUT signal) of the 16/32-bit reload timer...
  • Page 724CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.4.3. Operation in One-Shot Mode This section explains the operation in one-shot...
  • Page 725CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Figure 5-10 shows the output waveform in one-shot mode. Figure 5-10 Output...
  • Page 726CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.4.4. 32-bit Timer Mode Operation This section explains the 32-bit timer mode...
  • Page 727CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 3. When the down counter underflows, the UDIR bit of the base...
  • Page 728CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.4.5. Interrupts This section explains interrupts of the base timer. An interrupt...
  • Page 729CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.4.6. Precautions for Using this Device This section explains precautions for using...
  • Page 730CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.5. 16-bit PWM Timer Operation This section explains the 16-bit PWM timer...
  • Page 731CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.5.1. Overview This section explains the overview of the 16-bit PWM timer...
  • Page 732CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.5.2. Operation in Reload Mode This section explains the operation in reload...
  • Page 733CHAPTER 19: BASE TIMER 5. Operation MB91520 Series ⋅ If reactivation is not permitted (RTGEN = 0): Any activation trigger...
  • Page 734CHAPTER 19: BASE TIMER 5. Operation MB91520 Series  Output Waveform The waveform (TOUT signal) of the 16-bit PWM timer...
  • Page 735CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Note: ⋅ The output method and output destination of the waveform (TOUT...
  • Page 736CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.5.3. Operation in One-Shot Mode This section explains the operation in one-shot...
  • Page 737CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Figure 5-16 Counting Operation Counting operation when reactivation is disabled Rising edge...
  • Page 738CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.5.4. Interrupt This section explains interrupts. An interrupt request is generated in...
  • Page 739CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.5.5. Precautions for Using this Device This section explains precautions for using...
  • Page 740CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.6. 16-bit PPG Timer Operation This section explains the 16-bit PPG timer...
  • Page 741CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.6.1. Overview This section explains the overview of the 16-bit PPG timer...
  • Page 742CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.6.2. Pulse Width Calculation Method This section explains the pulse width calculation...
  • Page 743CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.6.3. Operation in Reload Mode This section explains the operation in reload...
  • Page 744CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Operation that is performed if reactivation is permitted or not during counting...
  • Page 745CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Notes: ⋅ The output method and output destination of the output signal...
  • Page 746CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Figure 5-19 Write Timing Rising edge detection Activation t rigger Trigger inter...
  • Page 747CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.6.4. Operation in One-Shot Mode This section explains the operation in one-shot...
  • Page 748CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Figure 5-21 Example of Counting Operation If Reactivation Is Not Enabled Rising...
  • Page 749CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Notes: ⋅ The output method and output destination of the output signal...
  • Page 750CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.6.5. Interrupts This section explains interrupts of the 16-bit PPG timer operation....
  • Page 751CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.6.6. Application Notes This section explains notes when using the 16-bit PPG...
  • Page 752CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.7. 16/32-bit PWC Timer Operation This section explains the 16/32-bit PWC timer...
  • Page 753CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Figure 5-24 Block Diagram (32-bit PWC Timer Operation) ch.1 BT1DTBF 16 Count...
  • Page 754CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.7.1. Overview This section explains the overview of the 16/32-bit PWC timer...
  • Page 755CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Table 5-6 Differences between Single and Continuous Measurement Modes Single measurement mode...
  • Page 756CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Figure 5-25 Operation Flow Select PWC mode Various settings Select count clock...
  • Page 757CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Note: In the continuous measurement mode, if the next measurement is completed...
  • Page 758CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Figure 5-27 Measurement Modes and their Explanation 2 Measurement mode (EGS2 to...
  • Page 759CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.7.2. Operation during PWC Measurement This section explains the operation during PWC...
  • Page 760CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Figure 5-28 Operation Example  Reactivation If the CTEN bit of the...
  • Page 761CHAPTER 19: BASE TIMER 5. Operation MB91520 Series Notes: ⋅ If a detection of measurement end edge and a timer...
  • Page 762CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.7.3. 32-bit Timer Mode Operation This section explains the 32-bit timer mode...
  • Page 763CHAPTER 19: BASE TIMER 5. Operation MB91520 Series The channel configuration in 32-bit timer mode is shown below. Figure 5-29...
  • Page 764CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.7.4. Interrupt This section explains interrupt of the base timer. An interrupt...
  • Page 765CHAPTER 19: BASE TIMER 5. Operation MB91520 Series 5.7.5. Application Notes This section explains application notes of the base timer....
  • Page 766CHAPTER 19: BASE TIMER 5. Operation MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 728 CHAPTER : BASE TIMER FUJITSU SEMICONDUCTOR CONFIDENTIAL...
  • Page 767: CHAPTER 20: RELOAD TIMERCHAPTER 20: RELOAD TIMER 1. Overview MB91520 Series CHAPTER : RELOAD TIMER This chapter explains the reload timer. 1. Overview...
  • Page 768CHAPTER 20: RELOAD TIMER 1. Overview MB91520 Series 1. Overview This section explains the overview of the reload timer. This...
  • Page 769CHAPTER 20: RELOAD TIMER 2. Features MB91520 Series 2. Features This section explains features of the reload timer. A 8-channel...
  • Page 770CHAPTER 20: RELOAD TIMER 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the reload timer. Figure...
  • Page 771CHAPTER 20: RELOAD TIMER 4. Registers MB91520 Series 4. Registers This section explains registers of the reload timer.  Table...
  • Page 772CHAPTER 20: RELOAD TIMER 4. Registers MB91520 Series  Registers Map Table 4-2 Registers Map Registers Address Register function +0...
  • Page 773 CHAPTER 20: RELOAD TIMER 4. Registers MB91520 Series 4.1. Control Status Register : TMCSR (TiMer Control and Status Register) The...
  • Page 774CHAPTER 20: RELOAD TIMER 4. Registers MB91520 Series [Interval timer mode, gate input (bit8:GATE =1)] Select the pin level which...
  • Page 775CHAPTER 20: RELOAD TIMER 4. Registers MB91520 Series [bit8] GATE (GATE input enable) : Gate input enabling bit This bit...
  • Page 776CHAPTER 20: RELOAD TIMER 4. Registers MB91520 Series [bit3] INTE (INTerrupt Enable) : Interrupt request enabling bit This bit controls...
  • Page 777 CHAPTER 20: RELOAD TIMER 4. Registers MB91520 Series 4.2. 16-bit Timer Register : TMR (16bit TiMer Register) The bit configuration...
  • Page 778 CHAPTER 20: RELOAD TIMER 4. Registers MB91520 Series 4.3. 16-bit Timer Reload Register A, 16-bit Timer Reload Register B :...
  • Page 779CHAPTER 20: RELOAD TIMER 4. Registers MB91520 Series TOUT output MOD[1:0] Mode RELD OUTL H width L width 0 TMRLRA+1...
  • Page 780CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5. Operation This section explains the operation of the reload timer. 5.1....
  • Page 781CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.1. Setting Setting of the reload timer is shown below. The operation...
  • Page 782CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.1.1. Count Source The count source of the reload timer is shown...
  • Page 783CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.1.2. Timer Underflow period The timer underflow period is shown below. Underflow...
  • Page 784CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.1.3. Trigger The trigger of the reload timer is shown below. The...
  • Page 785CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.1.4. Gate The gate of the reload timer is shown below. When...
  • Page 786CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.1.5. Counter Operation Selection The counter operation selection is shown below. Select...
  • Page 787CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.1.6. TOUT Pin Level Setting The TOUT Pin level setting is shown...
  • Page 788CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series Figure 5-2 TOUT Output Change in Each Event (2 / 3) Function...
  • Page 789CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.2. Operation Procedure Operation procedures are shown. 5.2.1. Activation 5.2.2. Retrigger 5.2.3....
  • Page 790CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.2.1. Activation Activation is shown below. Writing "1" into the bit1:CNTE bit...
  • Page 791CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series Figure 5-4 Timer Activation Peripheral clock CNTE (register) TIN (pin) TIN pin...
  • Page 792CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.2.2. Retrigger The retrigger is explained. The trigger which is generated during...
  • Page 793CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series Figure 5-5 Retrigger Operation Count clock TIN(pin) TIN pin effective edge TRG(register)...
  • Page 794CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.2.3. Underflow/Reload Underflow/reload is shown below. Underflow is defined as the timer...
  • Page 795CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.2.4. Generation of Interrupt Requests Generation of interrupt requests is shown below....
  • Page 796CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.2.5. Concurrent Operation of Register Write and a Timer Activation The concurrent...
  • Page 797CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.3. Operations of Each Counter Operations of each counter are shown. 5.3.1....
  • Page 798CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.3.1. Single One-shot Operation The single one-shot operation is shown below. When...
  • Page 799CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series Figure 5-7 Single One-shot Operation Count clock TTRG(pin) TIN (pin) TTRG TIN...
  • Page 800CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.3.2. Single Reload Operation The single reload operation is shown below. When...
  • Page 801CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series Figure 5-8 Single Reload Operation Timer reloaded TMRLRA TMRLRA TMRLRA TMRLRA TMRLRA...
  • Page 802CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.3.3. Dual One-shot Operation The dual one-shot operation is shown below. When...
  • Page 803CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series Figure 5-10 Dual One-shot Operation Count clock Underflow UF-A UF-B UF-A UF...
  • Page 804CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.3.4. Dual Reload Operation The dual one-shot operation is shown below. When...
  • Page 805CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series Figure 5-11 Dual Reload Operation Timer reloaded A:TMRLRA A B A B...
  • Page 806CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.3.5. Compare One-shot Operation The compare one-shot operation is shown below. When...
  • Page 807CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series Figure 5-13 Compare One-shot Operation (1 / 2) • Sets TMRLRB <...
  • Page 808CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series Figure 5-14 Compare One-shot Operation (2 / 2) • Sets TMRLRB =...
  • Page 809CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.3.6. Compare Reload Operation The compare reload operation is shown below. When...
  • Page 810CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series Figure 5-16 Compare Reload Operation (1 / 2) • Sets TMRLRB <...
  • Page 811CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series Figure 5-17 Compare Reload Operation (2 / 2) • Sets TMRLRB =...
  • Page 812CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.3.7. Capture Mode The capture mode is shown below. When bit15, bit14:MOD[1:0]...
  • Page 813CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series Figure 5-19 Flowchart of Trigger Input Features in Interval Timer Mode GATE=0...
  • Page 814CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series Figure 5-20 Flowchart in Event Counter Mode CSL [2:0] = 111 NO...
  • Page 815CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.4. Cascade Input Cascade input is shown below. When you select cascade...
  • Page 816CHAPTER 20: RELOAD TIMER 5. Operation MB91520 Series 5.5. Priority of Concurrent Operations The priority of concurrent operations is shown...
  • Page 817CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series 6. Application Note An application note is shown below. This section...
  • Page 818CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series Table 6-1 Example of Configuration Function MOD[1:0] RELD TMRLRA TMRLRB 00...
  • Page 819CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series 6.1. Single One-shot Timer The single one-shot timer is shown below....
  • Page 820CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series 2. When using TIN input as a gate input TMCSR TMRLRA...
  • Page 821CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series [Timer activation] Follow the steps below to activate the timer. ⋅...
  • Page 822CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series 6.2. Reload Timer The reload time is shown below. The reload...
  • Page 823CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series 2. When using TIN input as a gate input TMCSR TMRLRA...
  • Page 824CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series [Timer activation] Follow the steps below to activate the timer. ⋅...
  • Page 825CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series 6.3. PPG PPG is shown below. PPG is the feature which...
  • Page 826CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series [Configuration] To use the timer as PPG, configure as follows. 1....
  • Page 827CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series * 1: TIN effective level setting TRGM[1:0]= x0------Count only for TIN=L...
  • Page 828CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series 3. When using TIN input as a trigger input TMCSR TMRLRA...
  • Page 829CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series 6.4. PWM PWM is shown below. PWM is the feature which...
  • Page 830CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series 2. When using TIN input as a gate input TMCSR TMRLRA...
  • Page 831CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series 3. When using TIN input as a trigger input TMCSR TMRLRA...
  • Page 832CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series 6.5. PWC PWC is shown below. PWC is the feature to...
  • Page 833CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series Figure 6-6 Example of Operation (TRGM=01) TIN input TTRG input TMRLRA...
  • Page 834CHAPTER 20: RELOAD TIMER 6. Application Note MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 796 CHAPTER : RELOAD TIMER FUJITSU SEMICONDUCTOR...
  • Page 835: CHAPTER 21: 32-BIT FREE-RUN TIMERCHAPTER 21: 32-BIT FREE-RUN TIMER 1. Overview MB91520 Series CHAPTER : 32-BIT FREE-RUN TIMER This chapter explains the 32-bit free-run...
  • Page 836CHAPTER 21: 32-BIT FREE-RUN TIMER 1. Overview MB91520 Series 1. Overview This section explains the overview of the 32-bit free-run...
  • Page 837CHAPTER 21: 32-BIT FREE-RUN TIMER 2. Features MB91520 Series 2. Features This section explains the features of the 32-bit free-run...
  • Page 838CHAPTER 21: 32-BIT FREE-RUN TIMER 2. Features MB91520 Series 2.1. Functions of the 32-bit free-run timer The functions of the...
  • Page 839CHAPTER 21: 32-BIT FREE-RUN TIMER 2. Features MB91520 Series 2.2. Functions of the free-run timer selector The functions of the...
  • Page 840CHAPTER 21: 32-BIT FREE-RUN TIMER 3. Configuration MB91520 Series 3. Configuration This section explains configuration of the free-run timer. MN705-00010-1v0-E...
  • Page 841CHAPTER 21: 32-BIT FREE-RUN TIMER 3. Configuration MB91520 Series 3.1. Configuration diagram of the 32-bit free-run timer The configuration diagram...
  • Page 842CHAPTER 21: 32-BIT FREE-RUN TIMER 3. Configuration MB91520 Series 3.2. Configuration diagram of the free-run timer selector The configuration diagram...
  • Page 843CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4. Registers This section explains the registers of the free-run timer....
  • Page 844CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4.1. Registers of the 32-bit free-run timer The registers of the...
  • Page 845CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4.1.1. Timer Control Register (Upper Bit) : TCCSH The bit configuration...
  • Page 846CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit8] ICRE : Compare clear interrupt request enabled ICRE Operation 0...
  • Page 847CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4.1.2. Timer Control Register (Lower Bit) : TCCSL The bit configuration...
  • Page 848CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit3 to bit0] CLK3 to CLK0 : Clock frequency selection (when...
  • Page 849CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4.1.3. Compare Clear Register : CPCLR The bit configuration of the...
  • Page 850CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4.1.4. Timer Data Register : TCDT The bit configuration of the...
  • Page 851CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4.2. Registers of the free-run timer selector The registers of the...
  • Page 852CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4.2.1. Free-run timer selection register : FRS The bit configuration of...
  • Page 853CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit17, bit16] OS101, OS100 : free-run timer selector for output compare...
  • Page 854CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit7, bit6] : Undefined The read value is "0". Writing has...
  • Page 855CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series  FRS9: Address 0075H (Access: Byte, Half-word, Word) bit23 bit22 bit21...
  • Page 856CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit17, bit16] IS81, IS80 : free-run timer selector for input capture...
  • Page 857CHAPTER 21: 32-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit7, bit6] : Undefined The read value is "0". Writing has...
  • Page 858CHAPTER 21: 32-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5. Operation This section explains the operations of the free-run timer....
  • Page 859CHAPTER 21: 32-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.1. Operation of the 32-bit free-run timer This section shows the...
  • Page 860CHAPTER 21: 32-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.1.1. Count Operation This section shows the count operation. φ External...
  • Page 861CHAPTER 21: 32-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.1.2. Counting Up This section shows counting up. 32-bit free-run timer...
  • Page 862CHAPTER 21: 32-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.1.3. Timer Clear This section shows timer clear. The count value...
  • Page 863CHAPTER 21: 32-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.1.4. Each Clear Operations of the Free-run Timer This section shows...
  • Page 864CHAPTER 21: 32-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.1.5. Timer Interrupt This section shows timer interrupt. For the free-run...
  • Page 865CHAPTER 21: 32-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.2. Operation of the 32-bit free-run timer selector This section shows...
  • Page 866CHAPTER 21: 32-BIT FREE-RUN TIMER 6. Setting MB91520 Series 6. Setting This section explains setting of the free-run timer. Table...
  • Page 867CHAPTER 21: 32-BIT FREE-RUN TIMER 7. Q&A MB91520 Series 7. Q&A This section explains Q&A of the free-run timer. MN705-00010-1v0-E...
  • Page 868CHAPTER 21: 32-BIT FREE-RUN TIMER 7. Q&A MB91520 Series 7.1. How to Select Internal Clock Dividers? This section shows how...
  • Page 869CHAPTER 21: 32-BIT FREE-RUN TIMER 7. Q&A MB91520 Series 7.2. How to Select the External Clock? This section shows how...
  • Page 870CHAPTER 21: 32-BIT FREE-RUN TIMER 7. Q&A MB91520 Series 7.3. How to Enable/Disable the Count Operation of the Free-run Timer?...
  • Page 871CHAPTER 21: 32-BIT FREE-RUN TIMER 7. Q&A MB91520 Series 7.4. How to Clear the Free-run Timer? This section shows how...
  • Page 872CHAPTER 21: 32-BIT FREE-RUN TIMER 7. Q&A MB91520 Series 7.5. About Interrupt Related Registers? This section shows interrupt related registers....
  • Page 873CHAPTER 21: 32-BIT FREE-RUN TIMER 7. Q&A MB91520 Series 7.6. How to Enable Compare Clear Interrupt? This section shows how...
  • Page 874CHAPTER 21: 32-BIT FREE-RUN TIMER 7. Q&A MB91520 Series 7.7. How to Stop the Free-run Timer Operation? This section shows...
  • Page 875CHAPTER 21: 32-BIT FREE-RUN TIMER 8. Sample Program MB91520 Series 8. Sample Program This section explains sample program of the...
  • Page 876CHAPTER 21: 32-BIT FREE-RUN TIMER 9. Notes MB91520 Series 9. Notes This section explains notes of the free-run timer. ...
  • Page 877: CHAPTER 22: 32-BIT OUTPUT COMPARECHAPTER 22: 32-BIT OUTPUT COMPARE 1. Overview MB91520 Series CHAPTER : 32-BIT OUTPUT COMPARE This chapter explains the 32-bit output...
  • Page 878CHAPTER 22: 32-BIT OUTPUT COMPARE 1. Overview MB91520 Series 1. Overview This section explains the overview of the 32-bit output...
  • Page 879CHAPTER 22: 32-BIT OUTPUT COMPARE 2. Features MB91520 Series 2. Features This section explains the features of the 32-bit output...
  • Page 880CHAPTER 22: 32-BIT OUTPUT COMPARE 2. Features MB91520 Series ⋅ Type : 32-bit compare register × 4 + compare circuit...
  • Page 881CHAPTER 22: 32-BIT OUTPUT COMPARE 3. Configuration Diagram MB91520 Series 3. Configuration Diagram This section explains the configuration diagram of...
  • Page 882CHAPTER 22: 32-BIT OUTPUT COMPARE 4. Registers MB91520 Series 4. Registers This section explains the registers of the 32-bit output...
  • Page 883CHAPTER 22: 32-BIT OUTPUT COMPARE 4. Registers MB91520 Series 4.1. Output Control Register (Upper Bit) : OCSH The bit configuration...
  • Page 884CHAPTER 22: 32-BIT OUTPUT COMPARE 4. Registers MB91520 Series [bit9] OTD : Pin level setting (Output compare y) [bit8] OTD...
  • Page 885CHAPTER 22: 32-BIT OUTPUT COMPARE 4. Registers MB91520 Series 4.2. Output Control Register (Lower Bit) : OCSL The bit configuration...
  • Page 886CHAPTER 22: 32-BIT OUTPUT COMPARE 4. Registers MB91520 Series [bit1] CST : Operation enable (Output compare y) [bit0] CST :...
  • Page 887CHAPTER 22: 32-BIT OUTPUT COMPARE 4. Registers MB91520 Series 4.3. Compare Register : OCCP The bit configuration of the compare...
  • Page 888CHAPTER 22: 32-BIT OUTPUT COMPARE 4. Registers MB91520 Series 4.4. Output Level Control Register : OCLS The bit configuration of...
  • Page 889CHAPTER 22: 32-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5. Operation This section explains the operations of the 32-bit output...
  • Page 890CHAPTER 22: 32-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5.1. Output Compare Output (Independent Invert) CMOD = "0" This section...
  • Page 891CHAPTER 22: 32-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5.2. Output Compare Output (Coordinated Invert) CMOD = "1" This section...
  • Page 892CHAPTER 22: 32-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5.3. Output Compare Operation Timing This section shows the output compare...
  • Page 893CHAPTER 22: 32-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5.3.1. Compare Register Write Compare register write is shown below. The...
  • Page 894CHAPTER 22: 32-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5.3.2. Compare match, Interrupt Compare match, interrupt are shown below. Figure...
  • Page 895CHAPTER 22: 32-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5.3.3. Pin Output This section shows the pin output. Figure 5-3...
  • Page 896CHAPTER 22: 32-BIT OUTPUT COMPARE 6. Setting MB91520 Series 6. Setting This section explains settings of the 32-bit output compare....
  • Page 897CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7. Q&A This section explains Q&A of the 32-bit output compare....
  • Page 898CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.1. How Can I Set the Compare Value? This section shows...
  • Page 899CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.2. How Can I Set the Compare Mode? (Example with OCU7)...
  • Page 900CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.3. How Can I Enable/Disable the Compare Operation? (Example with OCU6,7)...
  • Page 901CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.4. How Can I Set the Compare Pin Output Initial Level?...
  • Page 902CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.5. How Can I Set the Compare Pin OCU6-OCU7 for Output?...
  • Page 903CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.6. How Can I Clear the Free-run Timer? This section shows...
  • Page 904CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.7. How Can I Enable the Compare Operation? (Example with OCU6,7)...
  • Page 905CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.8. Interrupt Related Register? This section shows the interrupt related register....
  • Page 906CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.9. Interrupt Type? This section shows the interrupt type. The interrupt...
  • Page 907CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.10. How Can I Enable the Interrupt? This section shows how...
  • Page 908CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.11. Calculation Method for the Compare Value? This section shows the...
  • Page 909CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.11.1. Toggle Output Pulse This section shows the toggle output pulse....
  • Page 910CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.11.2. PWM Output This section shows the PWM output. (Example) To...
  • Page 911CHAPTER 22: 32-BIT OUTPUT COMPARE 7. Q&A MB91520 Series 7.12. To Set the Operation Mode? This section shows how to...
  • Page 912CHAPTER 22: 32-BIT OUTPUT COMPARE 8. Sample Program MB91520 Series 8. Sample Program This section explains a sample program. Configuration...
  • Page 913CHAPTER 22: 32-BIT OUTPUT COMPARE 8. Sample Program MB91520 Series Configuration procedure example 2 Program example 2 .Compare for two...
  • Page 914CHAPTER 22: 32-BIT OUTPUT COMPARE 9. Notes MB91520 Series 9. Notes This section explains the notes of the 32-bit output...
  • Page 915: CHAPTER 23: 32-BIT INPUT CAPTURECHAPTER 23: 32-BIT INPUT CAPTURE 1. Overview MB91520 Series CHAPTER : 32-BIT INPUT CAPTURE This chapter explains the 32-bit input...
  • Page 916CHAPTER 23: 32-BIT INPUT CAPTURE 1. Overview MB91520 Series 1. Overview This section explains the overview of the 32-bit input...
  • Page 917CHAPTER 23: 32-BIT INPUT CAPTURE 2. Features MB91520 Series 2. Features This section explains features of the 32-bit input capture....
  • Page 918CHAPTER 23: 32-BIT INPUT CAPTURE 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the 32-bit input...
  • Page 919CHAPTER 23: 32-BIT INPUT CAPTURE 4. Registers MB91520 Series 4. Registers This section explains registers of the 32-bit input capture....
  • Page 920CHAPTER 23: 32-BIT INPUT CAPTURE 4. Registers MB91520 Series Table 4-2 Registers Map Registers Address Register function +0 +1 +2...
  • Page 921CHAPTER 23: 32-BIT INPUT CAPTURE 4. Registers MB91520 Series 4.1. Input Capture Data Register : IPCP This section shows the...
  • Page 922CHAPTER 23: 32-BIT INPUT CAPTURE 4. Registers MB91520 Series 4.2. Input Capture Control Register : ICS This section shows the...
  • Page 923CHAPTER 23: 32-BIT INPUT CAPTURE 4. Registers MB91520 Series 4.3. LIN SYNCH FIELD Switching Register : LSYNS This section shows...
  • Page 924CHAPTER 23: 32-BIT INPUT CAPTURE 4. Registers MB91520 Series 4.4. Cycle Measurement Data Register : MSCY This section shows the...
  • Page 925CHAPTER 23: 32-BIT INPUT CAPTURE 4. Registers MB91520 Series 4.5. Cycle and Pulse Width Measurement Control Register (Upper bit) :...
  • Page 926CHAPTER 23: 32-BIT INPUT CAPTURE 4. Registers MB91520 Series [bit9, bit8] OVPn : Pulse width measurement over flag OVPn Explanation...
  • Page 927CHAPTER 23: 32-BIT INPUT CAPTURE 4. Registers MB91520 Series 4.6. Cycle and Pulse Width Measurement Control Register (Lower bit) :...
  • Page 928CHAPTER 23: 32-BIT INPUT CAPTURE 5. Operation MB91520 Series 5. Operation This section explains the operation of the 32-bit input...
  • Page 929CHAPTER 23: 32-BIT INPUT CAPTURE 5. Operation MB91520 Series 5.1. Capture and Interrupt Timings This section shows capture and interrupts...
  • Page 930CHAPTER 23: 32-BIT INPUT CAPTURE 5. Operation MB91520 Series 5.2. Edge Detection Specifications for Input Capture And Their Operations This...
  • Page 931CHAPTER 23: 32-BIT INPUT CAPTURE 5. Operation MB91520 Series (11) Falling edge of the input signal is detected. (12) Free-run...
  • Page 932CHAPTER 23: 32-BIT INPUT CAPTURE 5. Operation MB91520 Series 5.3. Cycle and Pulse Width Measurement Operation This section shows the...
  • Page 933CHAPTER 23: 32-BIT INPUT CAPTURE 5. Operation MB91520 Series Figure 5-3 Example of the Cycle and Pulse Width Measurement Operation...
  • Page 934CHAPTER 23: 32-BIT INPUT CAPTURE 5. Operation MB91520 Series Figure 5-4 Example of the Cycle and Pulse Width Measurement Operation...
  • Page 935CHAPTER 23: 32-BIT INPUT CAPTURE 5. Operation MB91520 Series Figure 5-5 Example of the Cycle and Pulse Width Measurement Operation...
  • Page 936CHAPTER 23: 32-BIT INPUT CAPTURE 6. Setting MB91520 Series 6. Setting This section explains setting of the 32-bit input capture....
  • Page 937CHAPTER 23: 32-BIT INPUT CAPTURE 7. Q&A MB91520 Series 7. Q&A This section explains Q&A of the 32-bit input capture....
  • Page 938CHAPTER 23: 32-BIT INPUT CAPTURE 7. Q&A MB91520 Series 7.1. Effective Edge Polarity of External Input: Types and How to...
  • Page 939CHAPTER 23: 32-BIT INPUT CAPTURE 7. Q&A MB91520 Series 7.2. How to Enable External Input Pins (ICU4 to ICU9)? This...
  • Page 940CHAPTER 23: 32-BIT INPUT CAPTURE 7. Q&A MB91520 Series 7.3. About Interrupt Related Registers This section shows interrupt related registers....
  • Page 941CHAPTER 23: 32-BIT INPUT CAPTURE 7. Q&A MB91520 Series 7.4. About Interrupt Types This section shows interrupt types. There are...
  • Page 942CHAPTER 23: 32-BIT INPUT CAPTURE 7. Q&A MB91520 Series 7.5. How to Enable Interrupt? This section shows how to enable...
  • Page 943CHAPTER 23: 32-BIT INPUT CAPTURE 7. Q&A MB91520 Series 7.6. How to Measure the Pulse Width of the Input Signal?...
  • Page 944CHAPTER 23: 32-BIT INPUT CAPTURE 7. Q&A MB91520 Series 7.7. How to Set the Setting of the Operation Mode? This...
  • Page 945CHAPTER 23: 32-BIT INPUT CAPTURE 8. Sample Program MB91520 Series 8. Sample Program This section explains the sample program of...
  • Page 946CHAPTER 23: 32-BIT INPUT CAPTURE 9. Notes MB91520 Series 9. Notes This section explains notes of the 32-bit input capture....
  • Page 947: CHAPTER 24: 16-BIT FREE-RUN TIMERCHAPTER 24: 16-BIT FREE-RUN TIMER 1. Overview MB91520 Series CHAPTER : 16-BIT FREE-RUN TIMER This chapter explains the 16-bit free-run...
  • Page 948CHAPTER 24: 16-BIT FREE-RUN TIMER 1. Overview MB91520 Series 1. Overview This section is explains the overview of 16-bit free-run...
  • Page 949CHAPTER 24: 16-BIT FREE-RUN TIMER 2. Features MB91520 Series 2. Features This section is explains the features of 16-bit free-run...
  • Page 950CHAPTER 24: 16-BIT FREE-RUN TIMER 3. Configuration MB91520 Series 3. Configuration This section is explains the configuration of 16-bit free-run...
  • Page 951CHAPTER 24: 16-BIT FREE-RUN TIMER 3. Configuration MB91520 Series  Configuration of the 16-bit Free-run Timer Figure 3-2 Configuration of...
  • Page 952CHAPTER 24: 16-BIT FREE-RUN TIMER 3. Configuration MB91520 Series  Configuration of the Free-run Timer Selector Figure 3-3 Configuration of...
  • Page 953CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4. Registers This section is explains the registers of 16-bit free-run...
  • Page 954CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4.1. Registers for the Free-run Timer Simultaneous Activation Registers for the...
  • Page 955CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit0] GSCLR: Simultaneous timer clear bit Function GSCLR Read Write 0...
  • Page 956CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4.1.2. Timer Synchronous Activation Enable Register : TCGSE The timer synchronous...
  • Page 957CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4.2. Registers for the 16-bit Free-run Timer Registers for the 16-bit...
  • Page 958CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series  CPCLR0, 1, 2: Address 1204H, 120CH, 1214H (Access: Half-word, Word)...
  • Page 959CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4.2.2. Timer Data Register : TCDT0 to TCDT2 The timer data...
  • Page 960CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series Notes: The 16-bit free-run timer will not be initialized even when...
  • Page 961CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4.2.3. Timer State Control Register : TCCS0 to TCCS2 The timer...
  • Page 962CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit31] ECKE: Clock selection bit ECKE Function 0 Peripheral clock 1...
  • Page 963CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit29] IRQZE: 0 detection interrupt request enable bit IRQZE Function 0...
  • Page 964CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit25] ICLR: Compare clear interrupt flag bit Function ICLR Read Write...
  • Page 965CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit22] STOP: Timer enable bit STOP Function 0 Enable counting (Start...
  • Page 966CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit20] SCLR: Timer clear bit Function SCLR Read Write 0 Counter...
  • Page 967CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit11] MODE2 : Interrupt mask mode bit 2 MODE2 MODE* Function...
  • Page 968CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series Notes: The value read is a mask counter value. If a...
  • Page 969CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series 4.3. Register for the Free-run Timer Selector Register for the free-run...
  • Page 970CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit31 to bit22] Reserved Always write 0 to these bits. [bit21,...
  • Page 971CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit11, bit10] Reserved Always write 0 to this bit. [bit9, bit8]...
  • Page 972CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series  FRS1: Address 123AH (Access: Byte, Half-word, Word) bit15 bit14 bit13...
  • Page 973CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit5, bit4] IS11, IS10: Input capture free-run timer selector selection bits...
  • Page 974CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series  FRS2: Address 123CH (Access: Byte, Half-word, Word) bit31 bit30 bit29...
  • Page 975CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved AS91 AS90...
  • Page 976CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Reserved AS271 AS270...
  • Page 977CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series  FRS7: Address 12D8H (Access: Byte, Half-word, Word) bit31 bit30 bit29...
  • Page 978CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit25, bit24] AS461, AS460: A/D activation compare free-run timer selector selection...
  • Page 979CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit15, bit14] Reserved Always write 0 to this bit. [bit13, bit12]...
  • Page 980CHAPTER 24: 16-BIT FREE-RUN TIMER 4. Registers MB91520 Series [bit5, bit4] AS411, AS410: A/D activation compare free-run timer selector selection...
  • Page 981CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5. Operation The section explains the operation description of the 16-bit...
  • Page 982CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.1. Interrupt for the 16-bit Free-run Timer Interrupt for the 16-bit...
  • Page 983CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.2. Operation of the 16-bit Free-run Timer Operation of the 16-bit...
  • Page 984CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.2.2. Timer Mode For the 16-bit free-run timer, you will be...
  • Page 985CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.2.3. Compare Clear Buffer The compare clear register (CPCLR) has a...
  • Page 986CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series Figure 5-5 Operation in the Up/Down Count Mode when the Compare...
  • Page 987CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.2.4. Timer Interrupt For the 16-bit free-run timer, you will be...
  • Page 988CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.2.5. Interrupt Mask Function You can mask either or both of...
  • Page 989CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series Figure 5-9 0 Detection Interrupt Masked in the Up/Down Count Mode...
  • Page 990CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.2.6. Selected External Count Clock The 16-bit free-run timer will be...
  • Page 991CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.3. Operation of the Free-run Timer Selector Operation of the free-run...
  • Page 992CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series Resources Register Remarks ADT30 FRS5:AS30[1:0] ADT31 FRS5:AS31[1:0] ADT32 FRS6:AS32[1:0] ADT33 FRS6:AS33[1:0]...
  • Page 993CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.4. Notes on Operating Specifications Notes on operating specifications are explained....
  • Page 994CHAPTER 24: 16-BIT FREE-RUN TIMER 5. Operation MB91520 Series 5.4.3. Notes on Using the Free-run Timer Selector Be sure to...
  • Page 995: CHAPTER 25: 16-BIT OUTPUT COMPARECHAPTER 25: 16-BIT OUTPUT COMPARE 1. Overview MB91520 Series CHAPTER : 16-BIT OUTPUT COMPARE This chapter explains the 16-bit output...
  • Page 996CHAPTER 25: 16-BIT OUTPUT COMPARE 1. Overview MB91520 Series 1. Overview This section explains the overview of the 16-bit output...
  • Page 997CHAPTER 25: 16-BIT OUTPUT COMPARE 2. Features MB91520 Series 2. Features This section explains the features of the 16-bit output...
  • Page 998CHAPTER 25: 16-BIT OUTPUT COMPARE 3. Configuration Diagram MB91520 Series 3. Configuration Diagram This section explains the configuration diagram of...
  • Page 999CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series 4. Registers This section explains the registers of the 16-bit output...
  • Page 1000CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series 4.1. 16-bit Output Compare Registers This section explains the registers of...
  • Page 1001CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series 4.1.1. Output Compare Buffer Registers (OCCPB0 to OCCPB5)/Output Compare Registers (OCCP0...
  • Page 1002CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series • OCCPB1,3,5: Address 124EH, 1256H, 125EH (Access: Half-word, Word) bit15 bit14...
  • Page 1003CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series • OCCP0,2,4: Address124CH, 1254H, 125CH (Access: Half-word, Word) bit15 bit14 bit13...
  • Page 1004CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series • OCCP1,3,5: Address 124EH, 1256H, 125EH (Access: Half-word, Word) bit15 bit14...
  • Page 1005CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series 4.1.2. Compare Control Register (OCS) The bit configuration of the compare...
  • Page 1006CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series [bit13] BTS0: Buffer transfer selection bit BTS0 Function 0 Transfer is...
  • Page 1007CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series ⋅ This bit is used to switch the compare output level...
  • Page 1008CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series [bit8] OTD0: Output level bit Function OTD0 Read Write 0 The...
  • Page 1009CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series [bit6] IOP0: Compare match interrupt flag bi Function IOP0 Read Write...
  • Page 1010CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series [bit3] BUF1: Compare buffer invalidating bit BUF1 Function 0 Validates the...
  • Page 1011CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series 4.1.3. Compare Mode Control Register (OCMOD) The bit configuration of the...
  • Page 1012CHAPTER 25: 16-BIT OUTPUT COMPARE 4. Registers MB91520 Series [bit0] MOD0: Compare match mode setting bit MOD0 Function 0 Inverts...
  • Page 1013CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5. Operation This section explains the operations. 5.1. Interrupts for 16-bit...
  • Page 1014CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5.1. Interrupts for 16-bit Output Compare This section explains the interrupts...
  • Page 1015CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5.2. Operation of 16-bit Output Compare This section explains the operation...
  • Page 1016CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5.2.1. Operation of 16-bit Output Compare (Inverted Mode, MOD0= 0 in...
  • Page 1017CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series  The output level can be changed using a pair of...
  • Page 1018CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series  Output level when the compare buffer is invalid Figure 5-5...
  • Page 1019CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5.2.2. Operation of 16-bit Output Compare (Set/Reset Mode, MOD0 = 1...
  • Page 1020CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5.2.3. 16-bit Output Compare Timing This section explains the 16-bit output...
  • Page 1021CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5.2.4. Operation of 16-bit Output Compare and Free-run Timer This section...
  • Page 1022CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series  Case #1 where the free-run timer is in up/down count...
  • Page 1023CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series  Case #2 where the free-run timer is in up/down count...
  • Page 1024CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series  Case #3 where the free-run timer is in up/down count...
  • Page 1025CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series  Case #4 where the free-run timer is in up/down count...
  • Page 1026CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series  Case #5 where the free-run timer is in up/down count...
  • Page 1027CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series  Case #6 where the free-run timer is in up/down count...
  • Page 1028CHAPTER 25: 16-BIT OUTPUT COMPARE 5. Operation MB91520 Series 5.3. Notes on Using 16-bit Output Compare The notes on using...
  • Page 1029: CHAPTER 26: 16-BIT INPUT CAPTURECHAPTER 26: 16-BIT INPUT CAPTURE 1. Overview MB91520 Series CHAPTER : 16-BIT INPUT CAPTURE This chapter explains the 16-bit input...
  • Page 1030CHAPTER 26: 16-BIT INPUT CAPTURE 1. Overview MB91520 Series 1. Overview This section explains the overview of the 16-bit input...
  • Page 1031CHAPTER 26: 16-BIT INPUT CAPTURE 2. Features MB91520 Series 2. Features This section explains features of the 16-bit input capture....
  • Page 1032CHAPTER 26: 16-BIT INPUT CAPTURE 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the 16-bit input...
  • Page 1033CHAPTER 26: 16-BIT INPUT CAPTURE 4. Registers MB91520 Series 4. Registers This section explains registers of the 16-bit input capture....
  • Page 1034CHAPTER 26: 16-BIT INPUT CAPTURE 4. Registers MB91520 Series 4.1. 16-bit Input Capture Registers This section explains registers of the...
  • Page 1035CHAPTER 26: 16-BIT INPUT CAPTURE 4. Registers MB91520 Series 4.1.1. Input Capture Data Register : IPCP0 to IPCP3 This section...
  • Page 1036CHAPTER 26: 16-BIT INPUT CAPTURE 4. Registers MB91520 Series 4.1.2. Input Capture State Control Register : ICS The bit configuration...
  • Page 1037CHAPTER 26: 16-BIT INPUT CAPTURE 4. Registers MB91520 Series [bit8] IEI0: Effective edge indication bit IEI0 Function 0 A falling...
  • Page 1038CHAPTER 26: 16-BIT INPUT CAPTURE 4. Registers MB91520 Series Notes: ⋅ If a read-modify-write (RMW) instruction is executed, "1" is...
  • Page 1039CHAPTER 26: 16-BIT INPUT CAPTURE 4. Registers MB91520 Series 4.1.3. LIN SYNCH FIELD Switching Register : LSYNS The bit configuration...
  • Page 1040CHAPTER 26: 16-BIT INPUT CAPTURE 5. Operation MB91520 Series 5. Operation This section explains the operation. 5.1. Interrupts for 16-bit...
  • Page 1041CHAPTER 26: 16-BIT INPUT CAPTURE 5. Operation MB91520 Series 5.1. Interrupts for 16-bit Input Capture This section explains the interrupts...
  • Page 1042CHAPTER 26: 16-BIT INPUT CAPTURE 5. Operation MB91520 Series 5.2. Operation of 16-bit Input Capture The operation of 16-bit Input...
  • Page 1043CHAPTER 26: 16-BIT INPUT CAPTURE 5. Operation MB91520 Series 5.2.1. Operation of 16-bit Input Capture The operation of 16-bit Input...
  • Page 1044CHAPTER 26: 16-BIT INPUT CAPTURE 5. Operation MB91520 Series 5.2.2. 16-bit Input Capture Input Timing The operation of 16-bit Input...
  • Page 1045CHAPTER 26: 16-BIT INPUT CAPTURE 5. Operation MB91520 Series 5.3. Notes on Using the 16-bit Input Capture This section explains...
  • Page 1046CHAPTER 26: 16-BIT INPUT CAPTURE 5. Operation MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 1008 CHAPTER : 16-BIT INPUT CAPTURE FUJITSU...
  • Page 1047: CHAPTER 27: UP/DOWN COUNTERCHAPTER 27: UP/DOWN COUNTER 1. Overview MB91520 Series CHAPTER : UP/DOWN COUNTER This chapter explains the up/down counter. 1. Overview...
  • Page 1048CHAPTER 27: UP/DOWN COUNTER 1. Overview MB91520 Series 1. Overview This section explains the overview of the up/down counter. The...
  • Page 1049CHAPTER 27: UP/DOWN COUNTER 2. Features MB91520 Series 2. Features This section explains the features of the up/down counter. ·...
  • Page 1050CHAPTER 27: UP/DOWN COUNTER 2. Features MB91520 Series · Counting direction: The last counting direction (count up/count down) can be...
  • Page 1051CHAPTER 27: UP/DOWN COUNTER 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the up/down counter. ...
  • Page 1052CHAPTER 27: UP/DOWN COUNTER 3. Configuration MB91520 Series · Counter control register (CCR) This register controls the up/down counter. ·...
  • Page 1053CHAPTER 27: UP/DOWN COUNTER 4. Registers MB91520 Series 4. Registers This section explains the registers of the up/down counter. ...
  • Page 1054CHAPTER 27: UP/DOWN COUNTER 4. Registers MB91520 Series 4.1. Reload Compare Register (RCR0, RCR1) The bit configuration of the reload...
  • Page 1055CHAPTER 27: UP/DOWN COUNTER 4. Registers MB91520 Series 4.2. Up/Down Count Register (UDCR0, UDCR1) The bit configuration of the up/down...
  • Page 1056CHAPTER 27: UP/DOWN COUNTER 4. Registers MB91520 Series 4.3. Counter Control Register (CCR0, CCR1) The bit configuration of the counter...
  • Page 1057CHAPTER 27: UP/DOWN COUNTER 4. Registers MB91520 Series Notes: · If the counter is reset, the counting down direction is...
  • Page 1058CHAPTER 27: UP/DOWN COUNTER 4. Registers MB91520 Series CMS1 CMS0 Operation mode 0 0 Timer mode 0 1 Up/down count...
  • Page 1059CHAPTER 27: UP/DOWN COUNTER 4. Registers MB91520 Series Note: When this bit is written to "1", the reload compare register...
  • Page 1060CHAPTER 27: UP/DOWN COUNTER 4. Registers MB91520 Series [bit2] CGSC : Counter clear/gate selection bit This bit selects a function...
  • Page 1061CHAPTER 27: UP/DOWN COUNTER 4. Registers MB91520 Series 4.4. Counter Status Register (CSR0, CSR1) The bit configuration of the counter...
  • Page 1062CHAPTER 27: UP/DOWN COUNTER 4. Registers MB91520 Series [bit5] UDIE : Overflow/underflow interrupt enable bit This bit sets whether or...
  • Page 1063CHAPTER 27: UP/DOWN COUNTER 4. Registers MB91520 Series [bit2] UDFF : Underflow detection flag bit This bit indicates that the...
  • Page 1064CHAPTER 27: UP/DOWN COUNTER 5. Interrupt MB91520 Series 5. Interrupt This section shows the interrupt of the up/down counter. An...
  • Page 1065CHAPTER 27: UP/DOWN COUNTER 5. Interrupt MB91520 Series Notes: · Once an interrupt request is generated, the up/down counter stops...
  • Page 1066CHAPTER 27: UP/DOWN COUNTER 6. Operation and Setting Procedure Examples MB91520 Series 6. Operation and Setting Procedure Examples This section...
  • Page 1067CHAPTER 27: UP/DOWN COUNTER 6. Operation and Setting Procedure Examples MB91520 Series · Reload compare function This function is a...
  • Page 1068CHAPTER 27: UP/DOWN COUNTER 6. Operation and Setting Procedure Examples MB91520 Series  Clear Events The counter value is cleared...
  • Page 1069CHAPTER 27: UP/DOWN COUNTER 6. Operation and Setting Procedure Examples MB91520 Series Figure 6-2 Clear Event Occurrence Timing UDCR 0065H...
  • Page 1070CHAPTER 27: UP/DOWN COUNTER 6. Operation and Setting Procedure Examples MB91520 Series 6.1. Operation in Timer Mode This section explains...
  • Page 1071CHAPTER 27: UP/DOWN COUNTER 6. Operation and Setting Procedure Examples MB91520 Series Figure 6-3 Operation Performed When the Reload Function...
  • Page 1072CHAPTER 27: UP/DOWN COUNTER 6. Operation and Setting Procedure Examples MB91520 Series 6.2. Operation in Up/down Count Mode This section...
  • Page 1073CHAPTER 27: UP/DOWN COUNTER 6. Operation and Setting Procedure Examples MB91520 Series  Operation performed when the reload function is...
  • Page 1074CHAPTER 27: UP/DOWN COUNTER 6. Operation and Setting Procedure Examples MB91520 Series  Operation performed when the reload compare function...
  • Page 1075CHAPTER 27: UP/DOWN COUNTER 6. Operation and Setting Procedure Examples MB91520 Series 6.3. Operation in the Phase Difference Count Mode...
  • Page 1076CHAPTER 27: UP/DOWN COUNTER 6. Operation and Setting Procedure Examples MB91520 Series  Count Operation  Normal operation If the...
  • Page 1077CHAPTER 27: UP/DOWN COUNTER 6. Operation and Setting Procedure Examples MB91520 Series 6.4. Operation in the Phase Difference Count Mode...
  • Page 1078CHAPTER 27: UP/DOWN COUNTER 6. Operation and Setting Procedure Examples MB91520 Series  Count Operation  Normal operation If the...
  • Page 1079: CHAPTER 28: REAL-TIME CLOCK(RTC)CHAPTER 28: REAL-TIME CLOCK(RTC) 1. Overview MB91520 Series CHAPTER : REAL-TIME CLOCK(RTC) This chapter explains the real-time clock (RTC). 1....
  • Page 1080CHAPTER 28: REAL-TIME CLOCK(RTC) 1. Overview MB91520 Series 1. Overview This section explains the overview of the real-time clock (RTC)....
  • Page 1081CHAPTER 28: REAL-TIME CLOCK(RTC) 2. Features MB91520 Series 2. Features This section explains features of the real-time clock (RTC). ⋅...
  • Page 1082CHAPTER 28: REAL-TIME CLOCK(RTC) 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the real-time clock (RTC)....
  • Page 1083CHAPTER 28: REAL-TIME CLOCK(RTC) 4. Registers MB91520 Series 4. Registers This section explains registers of the real-time clock (RTC). Table...
  • Page 1084CHAPTER 28: REAL-TIME CLOCK(RTC) 4. Registers MB91520 Series 4.1. RTC Control Register : WTCR The bit configuration of the RTC...
  • Page 1085CHAPTER 28: REAL-TIME CLOCK(RTC) 4. Registers MB91520 Series [bit16] INT4 : 0.5 second interrupt request flag State INT4 Read Write...
  • Page 1086CHAPTER 28: REAL-TIME CLOCK(RTC) 4. Registers MB91520 Series [bit13] INTE2 : 1 hour interrupt request enable INTE2 Operation 0 1...
  • Page 1087CHAPTER 28: REAL-TIME CLOCK(RTC) 4. Registers MB91520 Series [bit7 to bit4] Reserved These bits must always be written to "0"....
  • Page 1088CHAPTER 28: REAL-TIME CLOCK(RTC) 4. Registers MB91520 Series 4.2. Sub-second Register : WTBR The bit configuration of the sub-second register...
  • Page 1089CHAPTER 28: REAL-TIME CLOCK(RTC) 4. Registers MB91520 Series Table 4-2 WTBR Setting Example RTC clock frequency WTBR Setting value 32kHz...
  • Page 1090CHAPTER 28: REAL-TIME CLOCK(RTC) 4. Registers MB91520 Series 4.3. Day/Hour/Minute/Second Register : WTDR/ WTHR/ WTMR/ WTSR The bit configuration of...
  • Page 1091CHAPTER 28: REAL-TIME CLOCK(RTC) 4. Registers MB91520 Series WTSR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 - - S5...
  • Page 1092CHAPTER 28: REAL-TIME CLOCK(RTC) 5. Operation MB91520 Series 5. Operation This section explains the operation of the real-time clock (RTC)....
  • Page 1093CHAPTER 28: REAL-TIME CLOCK(RTC) 5. Operation MB91520 Series (2) -Write the values of Day/ Hour/ Minute/ Second to Day/ Hour/...
  • Page 1094CHAPTER 28: REAL-TIME CLOCK(RTC) 6. Setting MB91520 Series 6. Setting This section explains setting of the real-time clock (RTC). Table...
  • Page 1095CHAPTER 28: REAL-TIME CLOCK(RTC) 7. Q&A MB91520 Series 7. Q&A This section explains Q&A of the real-time clock (RTC). 7.1....
  • Page 1096CHAPTER 28: REAL-TIME CLOCK(RTC) 7. Q&A MB91520 Series 7.1. How to Set the 0.5 Second Count Interval? This section explains...
  • Page 1097CHAPTER 28: REAL-TIME CLOCK(RTC) 7. Q&A MB91520 Series 7.2. How to Initialize the Real-time Clock? This section explains how to...
  • Page 1098CHAPTER 28: REAL-TIME CLOCK(RTC) 7. Q&A MB91520 Series 7.3. How to Set/Update Number of Days (Day) and Time (Hour/Minute/Second)? This...
  • Page 1099CHAPTER 28: REAL-TIME CLOCK(RTC) 7. Q&A MB91520 Series 7.4. How to Start/Stop the Count of the Real-time Clock? This section...
  • Page 1100CHAPTER 28: REAL-TIME CLOCK(RTC) 7. Q&A MB91520 Series 7.5. How to Confirm That the Real-time Clock Is Running? This section...
  • Page 1101CHAPTER 28: REAL-TIME CLOCK(RTC) 7. Q&A MB91520 Series 7.6. How to Know the Number of Days and Time? This section...
  • Page 1102CHAPTER 28: REAL-TIME CLOCK(RTC) 7. Q&A MB91520 Series 7.7. How to Stop the Real-time Clock? This section explains how to...
  • Page 1103CHAPTER 28: REAL-TIME CLOCK(RTC) 7. Q&A MB91520 Series 7.8. How to Calibrate the Real-time Clock? This section explains how to...
  • Page 1104CHAPTER 28: REAL-TIME CLOCK(RTC) 7. Q&A MB91520 Series 7.9. What Are Interrupt Related Registers? This section explains interrupt related registers....
  • Page 1105CHAPTER 28: REAL-TIME CLOCK(RTC) 7. Q&A MB91520 Series 7.10. What Are the Interrupt Types and How to Select Them? This...
  • Page 1106CHAPTER 28: REAL-TIME CLOCK(RTC) 7. Q&A MB91520 Series 7.11. How to Enable Interrupts? This section explains how to enable interrupts....
  • Page 1107CHAPTER 28: REAL-TIME CLOCK(RTC) 8. Sample Program MB91520 Series 8. Sample Program This section explains the sample program of the...
  • Page 1108CHAPTER 28: REAL-TIME CLOCK(RTC) 9. Notes MB91520 Series 9. Notes This section explains notes of the real-time clock. ⋅ The...
  • Page 1109: CHAPTER 29: RTC/WDT1 CALIBRATIONCHAPTER 29: RTC/WDT1 CALIBRATION 1. Overview MB91520 Series CHAPTER : RTC/WDT1 CALIBRATION This chapter explains the RTC/WDT1 calibration. 1. Overview...
  • Page 1110CHAPTER 29: RTC/WDT1 CALIBRATION 1. Overview MB91520 Series 1. Overview This section gives an overview of the RTC/WDT1 calibration. This...
  • Page 1111CHAPTER 29: RTC/WDT1 CALIBRATION 2. Features MB91520 Series 2. Features This section explains features of the RTC/WDT1 calibration. RTC Clock...
  • Page 1112CHAPTER 29: RTC/WDT1 CALIBRATION 3. Configuration MB91520 Series 3. Configuration This section explains configuration of the RTC/WDT1 calibration. Figure 3-1...
  • Page 1113CHAPTER 29: RTC/WDT1 CALIBRATION 4. Registers MB91520 Series 4. Registers This section explains the registers of the RTC/WDT1 calibration. Table...
  • Page 1114CHAPTER 29: RTC/WDT1 CALIBRATION 4. Registers MB91520 Series 4.1. Calibration Unit Control Register 0 : CUCR0 (Calibration Unit Control Register...
  • Page 1115CHAPTER 29: RTC/WDT1 CALIBRATION 4. Registers MB91520 Series [bit0] INTEN (calibration INTerrupt ENable) : Interrupt enable This bit sets whether...
  • Page 1116CHAPTER 29: RTC/WDT1 CALIBRATION 4. Registers MB91520 Series 4.2. Sub Clock Timer Data Register : CUTD0 (Calibration Unit Timer Data...
  • Page 1117CHAPTER 29: RTC/WDT1 CALIBRATION 4. Registers MB91520 Series 4.3. Main Oscillation Timer Result Register 0 : CUTR0 (Calibration Unit Timer...
  • Page 1118 CHAPTER 29: RTC/WDT1 CALIBRATION 4. Registers MB91520 Series 4.4. Calibration Unit Control Register 1 : CUCR1 (Calibration Unit Control Register...
  • Page 1119CHAPTER 29: RTC/WDT1 CALIBRATION 4. Registers MB91520 Series INTEN Interrupt 0 Disabled 1 Enabled MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 1081 CHAPTER...
  • Page 1120CHAPTER 29: RTC/WDT1 CALIBRATION 4. Registers MB91520 Series 4.5. CR Clock Timer Data Register : CUTD1 (Calibration Unit Timer Data...
  • Page 1121CHAPTER 29: RTC/WDT1 CALIBRATION 4. Registers MB91520 Series 4.6. Main Oscillation Timer Result Register 1 : CUTR1 (Calibration Unit Timer...
  • Page 1122CHAPTER 29: RTC/WDT1 CALIBRATION 5. Operation MB91520 Series 5. Operation This section explains operation. 5.1. Real-Time Clock (RTC) Calibration 5.2....
  • Page 1123CHAPTER 29: RTC/WDT1 CALIBRATION 5. Operation MB91520 Series 5.1. Real-Time Clock (RTC) Calibration This section shows real-time clock (RTC) calibration....
  • Page 1124CHAPTER 29: RTC/WDT1 CALIBRATION 5. Operation MB91520 Series 5.2. Measurement of Errors in CR Clock This section shows measurement of...
  • Page 1125CHAPTER 29: RTC/WDT1 CALIBRATION 5. Operation MB91520 Series 5.3. Note This section gives a note. The number of counts will...
  • Page 1126CHAPTER 29: RTC/WDT1 CALIBRATION 5. Operation MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 1088 CHAPTER : RTC/WDT1 CALIBRATION FUJITSU SEMICONDUCTOR CONFIDENTIAL...
  • Page 1127: CHAPTER 30: POWER CONSUMPTION CONTROLCHAPTER 30: POWER CONSUMPTION CONTROL 1. Overview MB91520 Series CHAPTER : POWER CONSUMPTION CONTROL This chapter explains the power consumption...
  • Page 1128CHAPTER 30: POWER CONSUMPTION CONTROL 1. Overview MB91520 Series 1. Overview This section gives an overview of the power consumption...
  • Page 1129CHAPTER 30: POWER CONSUMPTION CONTROL 2. Features MB91520 Series 2. Features This section explains features of the power consumption control....
  • Page 1130CHAPTER 30: POWER CONSUMPTION CONTROL 3. Configuration MB91520 Series 3. Configuration This section shows the configuration of the power consumption...
  • Page 1131CHAPTER 30: POWER CONSUMPTION CONTROL 3. Configuration MB91520 Series Figure 3-2 Block Diagram of Microcontroller Internal Control 1'b0 CPU sleep...
  • Page 1132CHAPTER 30: POWER CONSUMPTION CONTROL 4. Registers MB91520 Series 4. Registers This section shows the registers of the power consumption...
  • Page 1133CHAPTER 30: POWER CONSUMPTION CONTROL 4. Registers MB91520 Series 4.1. Standby Control Register: STBCR (STandby mode Control Register) The bit...
  • Page 1134CHAPTER 30: POWER CONSUMPTION CONTROL 4. Registers MB91520 Series [bit1, bit0] SLVL[1:0] (Standby LeVeL) : Standby level setting These bits...
  • Page 1135CHAPTER 30: POWER CONSUMPTION CONTROL 4. Registers MB91520 Series 4.2. PMU Control Register : PMUCTLR (Power Management Unit ConTroL register)...
  • Page 1136CHAPTER 30: POWER CONSUMPTION CONTROL 4. Registers MB91520 Series 4.3. PoWeR on TiMing Control Register : PWRTMCTL (PoWeR on TiMing...
  • Page 1137CHAPTER 30: POWER CONSUMPTION CONTROL 4. Registers MB91520 Series 4.4. PMU Interrupt Flag Register 0 : PMUINTF0 (Power Management Unit...
  • Page 1138CHAPTER 30: POWER CONSUMPTION CONTROL 4. Registers MB91520 Series 4.5. PMU Interrupt Flag Register 1 : PMUINTF1 (Power Management Unit...
  • Page 1139CHAPTER 30: POWER CONSUMPTION CONTROL 4. Registers MB91520 Series 4.6. PMU Interrupt Flag Register 2 : PMUINTF2 (Power Management Unit...
  • Page 1140CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5. Operation Operations of the power consumption control are explained. Features...
  • Page 1141CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.1. Clock Control This section shows the clock control of the...
  • Page 1142CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.1.1. Division Setting This section shows division setting of the clock....
  • Page 1143CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.1.2. Stopping of Unused Clocks This section shows stopping of unused...
  • Page 1144CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.2. List of Clocks Supplied in Low-power Consumption Mode The list...
  • Page 1145CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.3. Sleep Mode This section describes sleep mode. Sleep mode is...
  • Page 1146CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.3.1. CPU Sleep Mode This section describes CPU sleep mode. CPU...
  • Page 1147CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.3.2. Bus Sleep Mode This section describes bus sleep mode. Bus...
  • Page 1148CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.3.3. Configuration of Sleep Mode The configuration of sleep mode is...
  • Page 1149CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.3.4. Activation of Sleep mode Activation of sleep mode is described...
  • Page 1150CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.3.5. Wake Up from the Sleep Mode Wake up from the...
  • Page 1151CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.3.6. Effect of Sleep Mode Effect of sleep mode is described...
  • Page 1152CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.4. Standby Mode : Watch Mode This section describes standby mode:...
  • Page 1153CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.4.1. Configuration of Watch Mode The configuration of watch mode is...
  • Page 1154CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.4.2. Activation of Watch Mode Activation of watch mode is described...
  • Page 1155CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.4.3. Wake Up from the Watch Mode Wake up from the...
  • Page 1156CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.4.4. Effect of Watch Mode The effect of watch mode is...
  • Page 1157CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.5. Standby Mode : Watch Mode with power-shutdown This section describes...
  • Page 1158CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.5.1. Configuration of Watch Mode with power-shutdown The configuration of watch...
  • Page 1159CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.5.2. Activation of Watch Mode with power-shutdown Activation of watch mode...
  • Page 1160CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series Figure 5-1 Transition Sequence to Watch Mode with power-shutdown Microcontroller マイコン動作...
  • Page 1161CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.5.3. Wake Up from the Watch Mode with power-shutdown Wake up...
  • Page 1162CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series Figure 5-2 Restore Sequence from Watch Mode with power-shutdown Watch 時計(ShutDown)...
  • Page 1163CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.5.4. Effect of Watch Mode with power-shutdown The effect of watch...
  • Page 1164CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.6. Standby Mode : Stop Mode This section describes standby mode:...
  • Page 1165CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.6.1. Configuration of Stop Mode The configuration of stop mode is...
  • Page 1166CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.6.2. Activation of Stop Mode Activation of stop mode is described...
  • Page 1167CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.6.3. Wake Up from the Stop Mode Wake up from the...
  • Page 1168CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.6.4. Effect of Stop Mode The effect of stop mode is...
  • Page 1169CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.7. Standby Mode : Stop Mode with power-shutdown This section describes...
  • Page 1170CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.7.1. Configuration of Stop Mode with power-shutdown The configuration of stop...
  • Page 1171CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.7.2. Activation of Stop Mode with power-shutdown Activation of stop mode...
  • Page 1172CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series Figure 5-3 Transition Sequence to Stop Mode with power-shutdown MN705-00010-1v0-E FUJITSU...
  • Page 1173CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.7.3. Wake Up from the Stop Mode with power-shutdown Wake up...
  • Page 1174CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series Figure 5-4 Return Sequence from Stop Mode with power-shutdown STOP(ShutDown) Interrupt...
  • Page 1175CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.7.4. Effect of Stop Mode with power-shutdown The effect of stop...
  • Page 1176CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.8. Stop State of Microcontroller The stop state of the microcontroller...
  • Page 1177CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.9. Transition to Illegal Standby Mode Transition to illegal standby mode...
  • Page 1178CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series 5.10. Restrictions on Power-Shutdown and Normal Standby Control Restrictions on power-shutdown...
  • Page 1179CHAPTER 30: POWER CONSUMPTION CONTROL 5. Operation MB91520 Series *3: When standby (power-shutdown) transition is directed after the operating clock...
  • Page 1180CHAPTER 30: POWER CONSUMPTION CONTROL 6. Example of Use MB91520 Series 6. Example of Use Examples of activation of sleep...
  • Page 1181: CHAPTER 31: INTERNAL LOW-VOLTAGE DETECTION (INTERNAL POWER SUPPLY LOW-VOLTAGE DETECTION)CHAPTER 31: LOW-VOLTAGE DETECTION (INTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 1. Overview CHAPTER : INTERNAL LOW-VOLTAGE DETECTION (INTERNAL POWER SUPPLY LOW-VOLTAGE...
  • Page 1182CHAPTER 31: LOW-VOLTAGE DETECTION (INTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 1. Overview 1. Overview This section gives an overview of the...
  • Page 1183CHAPTER 31: LOW-VOLTAGE DETECTION (INTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 2. Features 2. Features This section explains features of the internal...
  • Page 1184CHAPTER 31: LOW-VOLTAGE DETECTION (INTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 3. Configuration 3. Configuration This section shows the configuration of the...
  • Page 1185CHAPTER 31: LOW-VOLTAGE DETECTION (INTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 4. Registers 4. Registers This section shows the registers of the...
  • Page 1186CHAPTER 31: LOW-VOLTAGE DETECTION (INTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 4. Registers 4.1. Internal Low-Voltage Detection Register : LVD (Low-Voltage Detect...
  • Page 1187CHAPTER 31: LOW-VOLTAGE DETECTION (INTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 4. Registers [bit3] LVD_OE (Low Voltage Detect power fall Output Enable)...
  • Page 1188CHAPTER 31: LOW-VOLTAGE DETECTION (INTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 5. Operation 5. Operation This section explains operations of the internal...
  • Page 1189CHAPTER 31: LOW-VOLTAGE DETECTION (INTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 5. Operation 5.1. Internal Low-voltage Detection The internal low-voltage detection is...
  • Page 1190CHAPTER 31: LOW-VOLTAGE DETECTION (INTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 6. Notes 6. Notes This section provides notes on the internal...
  • Page 1191: CHAPTER 32: LOW-VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION)CHAPTER 32: LOW-VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 1. Overview CHAPTER : LOW-VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION) This chapter...
  • Page 1192CHAPTER 32: LOW-VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 1. Overview 1. Overview This section gives an overview of the...
  • Page 1193CHAPTER 32: LOW-VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 2. Features 2. Features This section explains features of the low-voltage...
  • Page 1194CHAPTER 32: LOW-VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 3. Configuration 3. Configuration This section explains the configuration of the...
  • Page 1195CHAPTER 32: LOW-VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 4. Registers 4. Registers This section explains the registers of the...
  • Page 1196CHAPTER 32: LOW-VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 4. Registers 4.1. External Low-Voltage Detection Rise Detection Register : LVD5R...
  • Page 1197CHAPTER 32: LOW-VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 4. Registers 4.2. External Low-Voltage Detection Fall Detection Register : LVD5F...
  • Page 1198CHAPTER 32: LOW-VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 4. Registers LVD5F_SEL[3:0] External power supply fall detection voltage setting 0110...
  • Page 1199CHAPTER 32: LOW-VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 5. Operation 5. Operation This section explains operation of the low-voltage...
  • Page 1200CHAPTER 32: LOW-VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION) MB91520 Series 6. Notes 6. Notes This section provides notes on the low-voltage...
  • Page 1201: CHAPTER 33: WILD REGISTERCHAPTER 33: WILD REGISTER 1. Overview MB91520 Series CHAPTER : WILD REGISTER This chapter explains the wild register. 1. Overview...
  • Page 1202CHAPTER 33: WILD REGISTER 1. Overview MB91520 Series 1. Overview This section explains the overview of the wild register. The...
  • Page 1203CHAPTER 33: WILD REGISTER 2. Features MB91520 Series 2. Features This section explains features of the wild register. ⋅ Allows...
  • Page 1204CHAPTER 33: WILD REGISTER 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the wild register. Figure...
  • Page 1205CHAPTER 33: WILD REGISTER 4. Registers MB91520 Series 4. Registers This section explains registers of the wild register. Table 4-1...
  • Page 1206CHAPTER 33: WILD REGISTER 4. Registers MB91520 Series Registers Address Register function +0 +1 +2 +3 0x08E0 WRAR12 Wild register...
  • Page 1207CHAPTER 33: WILD REGISTER 4. Registers MB91520 Series 4.1. Wild Register Data Enable Register : WREN (Wild Register ENable register)...
  • Page 1208CHAPTER 33: WILD REGISTER 4. Registers MB91520 Series 4.2. Wild Register Address Register 00 to 15 : WRAR00 to 15...
  • Page 1209CHAPTER 33: WILD REGISTER 4. Registers MB91520 Series 4.3. Wild Register Data Register 00 to 15 : WRDR00 to 15...
  • Page 1210CHAPTER 33: WILD REGISTER 5. Operation MB91520 Series 5. Operation This section explains the operation of the wild register. This...
  • Page 1211CHAPTER 33: WILD REGISTER 6. Usage Example MB91520 Series 6. Usage Example This section explains a usage example of the...
  • Page 1212CHAPTER 33: WILD REGISTER 6. Usage Example MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 1174 CHAPTER : WILD REGISTER FUJITSU SEMICONDUCTOR...
  • Page 1213: CHAPTER 34: CLOCK SUPERVISORCHAPTER 34: CLOCK SUPERVISOR 1. Overview MB91520 Series CHAPTER : CLOCK SUPERVISOR This chapter explains the clock supervisor. 1. Overview...
  • Page 1214CHAPTER 34: CLOCK SUPERVISOR 1. Overview MB91520 Series 1. Overview This section explains the overview of the clock supervisor. If...
  • Page 1215CHAPTER 34: CLOCK SUPERVISOR 2. Configuration MB91520 Series 2. Configuration This section shows the configuration of the clock supervisor. The...
  • Page 1216CHAPTER 34: CLOCK SUPERVISOR 3. Register MB91520 Series 3. Register This section explains a register of the clock supervisor. Table...
  • Page 1217CHAPTER 34: CLOCK SUPERVISOR 3. Register MB91520 Series 3.1. Clock Supervisor Control Register : CSVCR(Clock SuperVisor Control Register) The bit...
  • Page 1218CHAPTER 34: CLOCK SUPERVISOR 3. Register MB91520 Series [bit5] SM (Sub clock Missing) : Sub clock stop When this bit...
  • Page 1219CHAPTER 34: CLOCK SUPERVISOR 3. Register MB91520 Series [bit2] SSVE (Sub clock SuperVisor Enable) : Sub clock supervisor enable When...
  • Page 1220CHAPTER 34: CLOCK SUPERVISOR 4. Operation MB91520 Series 4. Operation This section explains the operation of the clock supervisor. After...
  • Page 1221CHAPTER 34: CLOCK SUPERVISOR 4. Operation MB91520 Series 4.1. Initial State This section explains the initial state. When initial setting,...
  • Page 1222CHAPTER 34: CLOCK SUPERVISOR 4. Operation MB91520 Series 4.2. Stopping CR Oscillator and the Clock Supervisor Function This section explains...
  • Page 1223CHAPTER 34: CLOCK SUPERVISOR 4. Operation MB91520 Series 4.3. Re-enabling the Clock Supervisor This section explains re-enabling the clock supervisor....
  • Page 1224CHAPTER 34: CLOCK SUPERVISOR 4. Operation MB91520 Series 4.4. Sub Clock Mode This section explains the sub clock mode of...
  • Page 1225CHAPTER 34: CLOCK SUPERVISOR 4. Operation MB91520 Series 4.5. Stop Mode This section explains stop mode of the clock supervisor....
  • Page 1226CHAPTER 34: CLOCK SUPERVISOR 4. Operation MB91520 Series 4.6. Watch Mode This section explains watch mode.  Main Clock Supervisor...
  • Page 1227CHAPTER 34: CLOCK SUPERVISOR 4. Operation MB91520 Series 4.7. Checking the Reset Factor Using the Clock Supervisor Checking the reset...
  • Page 1228CHAPTER 34: CLOCK SUPERVISOR 4. Operation MB91520 Series 4.8. Return from CR Clock Return from the CR clock is shown....
  • Page 1229CHAPTER 34: CLOCK SUPERVISOR 4. Operation MB91520 Series 4.9. Sub Clock Mode Enabled by Setting SCKS Bit Sub clock mode...
  • Page 1230CHAPTER 34: CLOCK SUPERVISOR 4. Operation MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 1192 CHAPTER : CLOCK SUPERVISOR FUJITSU SEMICONDUCTOR CONFIDENTIAL...
  • Page 1231: CHAPTER 35: REGULATOR CONTROLCHAPTER 35: REGULATOR CONTROL 1. Overview MB91520 Series CHAPTER : REGULATOR CONTROL This chapter explains the overview, features and configurations...
  • Page 1232CHAPTER 35: REGULATOR CONTROL 1. Overview MB91520 Series 1. Overview This section explains the overview of the regulator control. The...
  • Page 1233CHAPTER 35: REGULATOR CONTROL 2. Features MB91520 Series 2. Features This section explains features of the regulator control. • The...
  • Page 1234CHAPTER 35: REGULATOR CONTROL 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the regulator control. Figure...
  • Page 1235CHAPTER 35: REGULATOR CONTROL 4. Register MB91520 Series 4. Register This section explains a register of the regulator control. Table...
  • Page 1236CHAPTER 35: REGULATOR CONTROL 4. Register MB91520 Series 4.1. Regulator Output Voltage Select Register : REGSEL (REGulator output voltage SELect...
  • Page 1237CHAPTER 35: REGULATOR CONTROL 4. Register MB91520 Series [bit3 to bit1] STRSEL[2:0] (STandby Regulator voltage SELect) These bits set the...
  • Page 1238CHAPTER 35: REGULATOR CONTROL 5. Operation MB91520 Series 5. Operation This section explains the operation of the regulator control. Before...
  • Page 1239: CHAPTER 36: EXTERNAL BUS INTERFACECHAPTER 36: EXTERNAL BUS INTERFACE 1. Overview MB91520 Series CHAPTER : EXTERNAL BUS INTERFACE This chapter explains the external bus...
  • Page 1240CHAPTER 36: EXTERNAL BUS INTERFACE 1. Overview MB91520 Series 1. Overview This section explains the overview of the external bus...
  • Page 1241CHAPTER 36: EXTERNAL BUS INTERFACE 2. Features MB91520 Series 2. Features This section explains the features of the external bus...
  • Page 1242CHAPTER 36: EXTERNAL BUS INTERFACE 3. Configuration MB91520 Series 3. Configuration This section shows the configuration of the external bus...
  • Page 1243CHAPTER 36: EXTERNAL BUS INTERFACE 4. Registers MB91520 Series 4. Registers This section explains the registers of the external bus...
  • Page 1244CHAPTER 36: EXTERNAL BUS INTERFACE 4. Registers MB91520 Series 4.1. CS Area Setting Registers: ASR0 to ASR3 (Area Setting Register...
  • Page 1245CHAPTER 36: EXTERNAL BUS INTERFACE 4. Registers MB91520 Series [bit31 to bit16] SADR[31:16] (Start ADdRess) : CS Area Start Address...
  • Page 1246CHAPTER 36: EXTERNAL BUS INTERFACE 4. Registers MB91520 Series [bit2] WREN (WRite ENable) : Write Enable This bit sets whether...
  • Page 1247CHAPTER 36: EXTERNAL BUS INTERFACE 4. Registers MB91520 Series 4.2. CS Bus Setting Registers: ACR0 to ACR3 (Area Configuration Register...
  • Page 1248CHAPTER 36: EXTERNAL BUS INTERFACE 4. Registers MB91520 Series [bit 31 to bit8] Reserved Always write "0" to these bits....
  • Page 1249CHAPTER 36: EXTERNAL BUS INTERFACE 4. Registers MB91520 Series 4.3. CS Wait Registers : AWR0 to AWR3 (Area Wait Register...
  • Page 1250CHAPTER 36: EXTERNAL BUS INTERFACE 4. Registers MB91520 Series [bit31 to bit28] Reserved Always write "0" to these bits. [bit27...
  • Page 1251CHAPTER 36: EXTERNAL BUS INTERFACE 4. Registers MB91520 Series [bit17, bit16] WRCV[1:0] (Write ReCoVery cycle) : Write Recovery Cycle WRCV[1:0]...
  • Page 1252CHAPTER 36: EXTERNAL BUS INTERFACE 4. Registers MB91520 Series [bit11, bit10] CSWR[1:0] (CSnX to WRnX setup cycle) : CSnX to...
  • Page 1253CHAPTER 36: EXTERNAL BUS INTERFACE 4. Registers MB91520 Series [bit5, bit4] ACS[1:0] (A00 to A21 to CSnX delay cycle) :...
  • Page 1254CHAPTER 36: EXTERNAL BUS INTERFACE 4. Registers MB91520 Series 4.4. External DMA Transfer Registers: DMAR0-3 (DMA transfer Register 0-3) The...
  • Page 1255CHAPTER 36: EXTERNAL BUS INTERFACE 4. Registers MB91520 Series [bit1] ACKL When writing, always write "0" to this bit. [bit0]...
  • Page 1256CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5. Operation This section explains the operation of the external bus...
  • Page 1257CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.1. External Pin Table This section shows the external pin table....
  • Page 1258CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series External Pin number of pin of this this series Description series...
  • Page 1259CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.2. External Bus Signal Protocol This section shows the external bus...
  • Page 1260CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series  Signal description External bus output signals are synchronized to the...
  • Page 1261CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.2.2. Address/Data split bus write protocol This section shows the protocol...
  • Page 1262CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series ASX Indicates the start of access. This also functions as the...
  • Page 1263CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series  Operating example description cycle1 : "L" is output to ASX...
  • Page 1264CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.2.4. Address/Data multiplexed bus write protocol This section shows the protocol...
  • Page 1265CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series  Operating example description cycle1 : The cycle where access begins....
  • Page 1266CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.3. Address Alignment This section shows the address alignment. The external...
  • Page 1267CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.4. Split Access This section shows the split access. If the...
  • Page 1268CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.5. Data Alignment This section shows the data alignment. Each CS...
  • Page 1269CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series Access Output pins Split Address access D23 to Size lowermost A01,...
  • Page 1270CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series Table 5-6 Little endian - 8 bits Access Output pins Address...
  • Page 1271CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.6. Address Information This section shows the address information. 5.6.1. Address...
  • Page 1272CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.7. Idle Cycle Insertion Function This section shows the idle cycle...
  • Page 1273CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.8. External Bus Output Signal Timing Settings This section shows the...
  • Page 1274CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series Table 5-8 Address/Data split bus timing parameters Parameter name Function name...
  • Page 1275CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series  Address/Data multiplexed bus timing parameters This section shows the timing...
  • Page 1276CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series Table 5-9 Address/Data multiplexed bus timing parameters Parameter name Function name...
  • Page 1277CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series Number of write access cycles = Address output (1) + ACS(0...
  • Page 1278CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.9. RDY Pin Access Cycle Extension Function This section shows the...
  • Page 1279CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.10. CS Setting Flow This section explains the CS setting method....
  • Page 1280CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series The flow for configuring CS is shown below. Figure 5-9 CS...
  • Page 1281CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series Figure 5-10 Parameters that can be configured in AWR SYSCLK ASCY...
  • Page 1282CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series Table 5-10 List of parameter Parameter name Description Sets the auto...
  • Page 1283CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series The above setting values are written to ASR as words. The...
  • Page 1284CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series  The size of the CS area and the setting of...
  • Page 1285CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series • CS2 settings To allocate the space from 0x00110000 to 1MByte:...
  • Page 1286CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series Figure 5-12 CS1 Settings Sample Program  ACR1 Setting Example ...
  • Page 1287CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.11. Example of Connecting to Asynchronous Memory This section shows an...
  • Page 1288CHAPTER 36: EXTERNAL BUS INTERFACE 5. Operation MB91520 Series 5.12. Example of Connection to Little Endian Device This section shows...
  • Page 1289: CHAPTER 37: BUS PERFORMANCE COUNTERSCHAPTER 37: BUS PERFORMANCE COUNTERS 1. Overview MB91520 Series CHAPTER : BUS PERFORMANCE COUNTERS This chapter explains the bus performance...
  • Page 1290CHAPTER 37: BUS PERFORMANCE COUNTERS 1. Overview MB91520 Series 1. Overview This section explains the overview of the bus performance...
  • Page 1291CHAPTER 37: BUS PERFORMANCE COUNTERS 2. Features MB91520 Series 2. Features This section explains the features of the bus performance...
  • Page 1292CHAPTER 37: BUS PERFORMANCE COUNTERS 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the bus performance...
  • Page 1293CHAPTER 37: BUS PERFORMANCE COUNTERS 4. Registers MB91520 Series 4. Registers This section explains the registers of the bus performance...
  • Page 1294CHAPTER 37: BUS PERFORMANCE COUNTERS 4. Registers MB91520 Series 4.1. BPC-A Control Register : BPCCRA (Bus Performance Counter Control Register...
  • Page 1295CHAPTER 37: BUS PERFORMANCE COUNTERS 4. Registers MB91520 Series [bit1, bit0] SLV[1:0] (SLaVe select) : Slave selection These bits select...
  • Page 1296CHAPTER 37: BUS PERFORMANCE COUNTERS 4. Registers MB91520 Series 4.2. BPC-B Control Register : BPCCRB (Bus Performance Counter Control Register...
  • Page 1297CHAPTER 37: BUS PERFORMANCE COUNTERS 4. Registers MB91520 Series 4.3. BPC-C Control Register : BPCCRC (Bus Performance Counter Control Register...
  • Page 1298CHAPTER 37: BUS PERFORMANCE COUNTERS 4. Registers MB91520 Series 4.4. BPC-A Count Register : BPCTRA (Bus Performance CounTer Register A)...
  • Page 1299CHAPTER 37: BUS PERFORMANCE COUNTERS 4. Registers MB91520 Series 4.5. BPC-B Count Register : BPCTRB (Bus Performance CounTer Register B)...
  • Page 1300CHAPTER 37: BUS PERFORMANCE COUNTERS 4. Registers MB91520 Series 4.6. BPC-C Count Register : BPCTRC (Bus Performance CounTer Register C)...
  • Page 1301CHAPTER 37: BUS PERFORMANCE COUNTERS 5. Operation MB91520 Series 5. Operation This section explains the operations. 5.1. Setting 5.2. Starting...
  • Page 1302CHAPTER 37: BUS PERFORMANCE COUNTERS 5. Operation MB91520 Series 5.1. Setting This section explains the setting. Before starting each of...
  • Page 1303CHAPTER 37: BUS PERFORMANCE COUNTERS 5. Operation MB91520 Series FUNC[1:0] MST[3:0] SLV[1:0] Target event 00 Wait cycle of XBS, DMAC...
  • Page 1304CHAPTER 37: BUS PERFORMANCE COUNTERS 5. Operation MB91520 Series 5.2. Starting and Stopping This section explains the starting and stopping....
  • Page 1305CHAPTER 37: BUS PERFORMANCE COUNTERS 5. Operation MB91520 Series 5.3. Operation This section explains the operation. Once operation has been...
  • Page 1306CHAPTER 37: BUS PERFORMANCE COUNTERS 5. Operation MB91520 Series 5.4. Measurement and Result Processing This section explains the measurement and...
  • Page 1307CHAPTER 37: BUS PERFORMANCE COUNTERS 5. Operation MB91520 Series Analyze the measurement results using a debugger host program, such as...
  • Page 1308CHAPTER 37: BUS PERFORMANCE COUNTERS 5. Operation MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 1270 CHAPTER : BUS PERFORMANCE COUNTERS FUJITSU...
  • Page 1309: CHAPTER 38: CRCCHAPTER 38: CRC 1. Overview MB91520 Series CHAPTER : CRC This chapter explains the CRC. 1. Overview 2. Features 3....
  • Page 1310CHAPTER 38: CRC 1. Overview MB91520 Series 1. Overview This section explains the overview of the CRC. This module calculates...
  • Page 1311CHAPTER 38: CRC 2. Features MB91520 Series 2. Features This section explains features of the CRC. This module calculates CCITT...
  • Page 1312CHAPTER 38: CRC 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the CRC. Figure 3-1 Block...
  • Page 1313CHAPTER 38: CRC 4. Registers MB91520 Series 4. Registers This section explains registers of the CRC. Table 4-1 Registers Map...
  • Page 1314CHAPTER 38: CRC 4. Registers MB91520 Series 4.1. CRC Control Register : CRCCR (CRC Control Register) The bit configuration of...
  • Page 1315CHAPTER 38: CRC 4. Registers MB91520 Series 4.2. CRC Initial Value Register : CRCINIT (CRC Initial value register) The bit...
  • Page 1316CHAPTER 38: CRC 4. Registers MB91520 Series 4.3. CRC Input Data Register : CRCIN (CRC INput data register) The bit...
  • Page 1317CHAPTER 38: CRC 4. Registers MB91520 Series 4.4. CRC Register : CRCR (CRC Register) The bit configuration of the CRC...
  • Page 1318CHAPTER 38: CRC 5. Operation MB91520 Series 5. Operation This section explains the CRC. 5.1. CRC Definition 5.2. Reset Operation...
  • Page 1319CHAPTER 38: CRC 5. Operation MB91520 Series 5.1. CRC Definition The CRC definition is shown below.  CCITT CRC16 Standard...
  • Page 1320CHAPTER 38: CRC 5. Operation MB91520 Series 5.2. Reset Operation The reset operation of the CRC is shown below. To...
  • Page 1321CHAPTER 38: CRC 5. Operation MB91520 Series 5.3. Initialization The initialization of the CRC is shown below. In initialization by...
  • Page 1322CHAPTER 38: CRC 5. Operation MB91520 Series 5.4. Byte and Bit Orders The byte and bit orders of the CRC...
  • Page 1323CHAPTER 38: CRC 5. Operation MB91520 Series 5.5. CRC Calculation Sequence The CRC calculation sequence is shown below. The sequence...
  • Page 1324CHAPTER 38: CRC 5. Operation MB91520 Series 5.6. Examples The examples is shown below. 5.6.1. Example 1 CRC16, Fixed Byte...
  • Page 1325CHAPTER 38: CRC 5. Operation MB91520 Series 5.6.1. Example 1 CRC16, Fixed Byte Input Example 1 CRC16 and fixed byte...
  • Page 1326CHAPTER 38: CRC 5. Operation MB91520 Series ⋅ Bytes and half words can be written into any position. In this...
  • Page 1327CHAPTER 38: CRC 5. Operation MB91520 Series 5.6.2. Example 2 CRC16, Mixture of Different Input Bit Widths Example 2 CRC16...
  • Page 1328CHAPTER 38: CRC 5. Operation MB91520 Series 5.6.3. Example 3 CRC32, Byte Order, Big-endian Example 3 CRC32, the byte order...
  • Page 1329CHAPTER 38: CRC 5. Operation MB91520 Series 5.6.4. Example 4 CRC32, Byte Order, Little-endian Example 4 CRC32, the byte order...
  • Page 1330CHAPTER 38: CRC 5. Operation MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 1292 CHAPTER : CRC FUJITSU SEMICONDUCTOR CONFIDENTIAL 23
  • Page 1331: CHAPTER 39: RAMECCCHAPTER 39: RAMECC 1. Overview MB91520 Series CHAPTER : RAMECC This chapter explains the RAMECC function. 1. Overview 2. Features...
  • Page 1332CHAPTER 39: RAMECC 1. Overview MB91520 Series 1. Overview This section gives an overview of the RAMECC. The function of...
  • Page 1333CHAPTER 39: RAMECC 2. Features MB91520 Series 2. Features This section explains features of the RAMECC.  Target RAM ·...
  • Page 1334CHAPTER 39: RAMECC 3. Configuration MB91520 Series 3. Configuration This section shows the configuration of the RAMECC. Figure 3-1 Block...
  • Page 1335CHAPTER 39: RAMECC 4. Registers MB91520 Series 4. Registers This section explains the registers of the RAMECC. Table 4-1 Registers...
  • Page 1336CHAPTER 39: RAMECC 4. Registers MB91520 Series 4.1. Single-bit ECC Error Address Register XBS RAM : SEEARX The bit configuration...
  • Page 1337CHAPTER 39: RAMECC 4. Registers MB91520 Series 4.2. Double-bit ECC Error Address Register XBS RAM : DEEARX The bit configuration...
  • Page 1338CHAPTER 39: RAMECC 4. Registers MB91520 Series 4.3. ECC Error Control Register XBS RAM : EECSRX The bit configuration of...
  • Page 1339CHAPTER 39: RAMECC 4. Registers MB91520 Series 4.4. ECC False Error Generation Address Register XBS RAM : EFEARX The bit...
  • Page 1340CHAPTER 39: RAMECC 4. Registers MB91520 Series 4.5. ECC False Error Generation Control Register XBS RAM : EFECRX The bit...
  • Page 1341CHAPTER 39: RAMECC 4. Registers MB91520 Series [bit15 to bit8] EY7 to EY0 : False error generation byte setting bits...
  • Page 1342CHAPTER 39: RAMECC 4. Registers MB91520 Series 4.6. Single-bit ECC Error Address Register BACKUP-RAM : SEEARA The bit configuration of...
  • Page 1343CHAPTER 39: RAMECC 4. Registers MB91520 Series 4.7. Double-bit ECC Error Address Register BACKUP-RAM : DEEARA The bit configuration of...
  • Page 1344CHAPTER 39: RAMECC 4. Registers MB91520 Series 4.8. ECC Error Control Register BACKUP-RAM : EECSRA The bit configuration of the...
  • Page 1345CHAPTER 39: RAMECC 4. Registers MB91520 Series 4.9. ECC False Error Generation Address Register BACKUP-RAM : EFEARA The bit configuration...
  • Page 1346CHAPTER 39: RAMECC 4. Registers MB91520 Series 4.10. ECC False Error Generation Control Register BACKUP-RAM : EFECRA The bit configuration...
  • Page 1347CHAPTER 39: RAMECC 4. Registers MB91520 Series [bit15 to bit8] EY7 to EY0 : False error generation byte setting bits...
  • Page 1348CHAPTER 39: RAMECC 5. Operation MB91520 Series 5. Operation This section explains operations. 5.1. RAMECC Function 5.2. Interrupt-related Register 5.3....
  • Page 1349CHAPTER 39: RAMECC 5. Operation MB91520 Series 5.1. RAMECC Function The RAMECC function is explained. The RAMECC always functions (It,...
  • Page 1350CHAPTER 39: RAMECC 5. Operation MB91520 Series 5.2. Interrupt-related Register This section explains the interrupt-related register. Write "1" in the...
  • Page 1351CHAPTER 39: RAMECC 5. Operation MB91520 Series 5.3. Test Mode The test mode is explained. In this mode an ECC...
  • Page 1352CHAPTER 39: RAMECC 5. Operation MB91520 Series 5.4. Note This section explains note. A single bit error might be detected...
  • Page 1353: CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACECHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 1. Overview MB91520 Series CHAPTER : MULTI-FUNCTION SERIAL INTERFACE This chapter explains the multi-function serial...
  • Page 1354CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 1. Overview MB91520 Series 1. Overview This section explains the overview of the multi-function serial...
  • Page 1355CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 2. Features MB91520 Series 2. Features This section explains features of the multi-function serial interface....
  • Page 1356CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 2. Features MB91520 Series  UART UART (asynchronous serial interface) is the general-purpose serial data...
  • Page 1357CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 2. Features MB91520 Series  CSIO CSIO (Clock Synchronous Serial Interface) is a general-purpose serial...
  • Page 1358CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 2. Features MB91520 Series  LIN-UART  Manual Mode LIN-UART (LIN Communication Control UART) provides...
  • Page 1359CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 2. Features MB91520 Series  Assist Mode LIN-UART (LIN Communication Control UART) provides specific functions...
  • Page 1360CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 2. Features MB91520 Series Item Function ⋅ Transmission/reception FIFO equipped (transmission FIFO: 64 bytes, reception...
  • Page 1361CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 2. Features MB91520 Series  I2C I2C interface supports buses among ICs, and runs as...
  • Page 1362CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 3. Configuration MB91520 Series 3. Configuration This section explains configuration of the multi-function serial interface....
  • Page 1363CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 3. Configuration MB91520 Series Figure 3-2 Block Diagram (CSIO) Operation mode 2 (CSIO) MN705-00010-1v0-E FUJITSU...
  • Page 1364CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 3. Configuration MB91520 Series Figure 3-3 Block Diagram (LIN-UART) Operation mode 3 (LIN-UART) MN705-00010-1v0-E FUJITSU...
  • Page 1365CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 3. Configuration MB91520 Series Figure 3-4 Block Diagram (I2C) Operation mode 4 (I2C) MN705-00010-1v0-E FUJITSU...
  • Page 1366CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4. Registers This section explains registers of the multi-function serial interface....
  • Page 1367CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series  Registers Map Table 4-2 Registers Map Registers Address Registers function...
  • Page 1368CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Registers Address Registers function +0 +1 +2 +3 [UART] [UART] [UART]...
  • Page 1369CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.1. Common Registers Common registers are shown. MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED...
  • Page 1370CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.1.1. Serial Mode Register: SMR This register selects the serial communication...
  • Page 1371CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series When this bit is set to "0": ⋅ Serial clock output...
  • Page 1372CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [I2C] ⋅ This bit enables or disables the output of transmission...
  • Page 1373CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.1.2. FIFO Control Register 1: FCR1 FIFO control register (FCR1) is...
  • Page 1374CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Notes: ⋅ When transmission FIFO is enabled, writing "0" to this...
  • Page 1375CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.1.3. FIFO Control Register 0: FCR0 FIFO control register 0 (FCR0)...
  • Page 1376CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit3] FCL2 (FIFO Clear 2): FIFO2 reset bit This bit resets...
  • Page 1377CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit0] FE1 (FIFO Enable 1) FIFO1 operation enable bit This bit...
  • Page 1378CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.1.4. FIFO BYTE Register: FBYTE Function of this register changes for...
  • Page 1379CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Notes: ⋅ [UART] [LIN-UART] Set FBYTE register of the transmission FIFO...
  • Page 1380CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.1.5. Transmission FIFO Interrupt Control Register: FTICR Transmission FIFO interrupt control...
  • Page 1381CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.2. Registers for UART Registers for UART are shown. MN705-00010-1v0-E FUJITSU...
  • Page 1382CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.2.1. Serial Control Register: SCR The serial control register (SCR) allows...
  • Page 1383CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit1 RXE: This bit enables/disables the reception of...
  • Page 1384CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.2.2. Serial Status Register: SSR The serial status register (SSR) allows...
  • Page 1385CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit3 ORE: "0" Read: No overrun error. Overrun...
  • Page 1386CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit0 TBI: "0" Read: Transmission is in progress...
  • Page 1387CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.2.3. Extended Serial Control Register: ESCR The extended communication control register...
  • Page 1388CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit2, L2, L1, L0: These bits specify the...
  • Page 1389CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.2.4. Receive Data Register/Transmit Data Register: RDR/TDR The receive data register...
  • Page 1390CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series  Write  TDR0n(n=0 to 11): Address Base addr + 06H...
  • Page 1391CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.2.5. Serial Aid Control Status Register: SACSR Serial Aid Control Status...
  • Page 1392CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Notes: ⋅ Performing software reset (SCR:UPCL="1") will reset this bit to...
  • Page 1393CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Timer Operating Clock TDIV3 TDIV2 TDIV1 TDIV0 Division φ= φ= φ=...
  • Page 1394CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.2.6. Serial Timer Register: STMR Serial Timer Register (STMR) indicates the...
  • Page 1395CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.2.7. Serial timer Comparison Register: STMCR Serial Timer Comparison Register (STMCR)...
  • Page 1396CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.2.8. Transfer Byte Register: TBYTE Transfer Byte Register (TBYTE) indicates the...
  • Page 1397CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.2.9. Baud rate Generator Register: BGR Baud rate generator register (BGR)...
  • Page 1398CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.3. Registers for CSIO Registers for CSIO are shown. MN705-00010-1v0-E FUJITSU...
  • Page 1399CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.3.1. Serial Control Register: SCR The serial control register (SCR) allows...
  • Page 1400CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit5 SPI: This bit is used to execute...
  • Page 1401CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.3.2. Serial Status Register: SSR The serial status register (SSR) allows...
  • Page 1402CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit2 RDRF: "0" Read: Receive data register (RDR)...
  • Page 1403CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.3.3. Extended Serial Control Register: ESCR The extended communication control register...
  • Page 1404CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit6, L3, L2, L1, L0: These bits specify...
  • Page 1405CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.3.4. Receive Data Register/Transmit Data Register: RDR/TDR The receive data register...
  • Page 1406CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Example: When you read "AAAA5555"h with 32 bits data length: Number...
  • Page 1407CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series  Write  TDR1n-0n(n=0 to 11) : Address Base addr +...
  • Page 1408CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Example: When you write "AAAA5555"h with 32 bits data length: Number...
  • Page 1409CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.3.5. Serial Aid Control Status Register: SACSR The serial aid control...
  • Page 1410CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit12] CSEIE: Chip select error interrupt enable bit This bit is...
  • Page 1411CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Notes: ⋅ When software reset is triggered (SCR:UPCL="1"), this bit will...
  • Page 1412CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit4 to bit1] TDIV3-0: Timer operating clock division bits These bits...
  • Page 1413CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.3.6. Serial Timer Register: STMR The serial timer register (STMR) is...
  • Page 1414CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.3.7. Serial Timer Compare Register: STMCR The serial timer compare register...
  • Page 1415CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.3.8. Serial Chip Select Control Status Register: SCSCR The serial chip...
  • Page 1416CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Notes: ⋅ These bits can be changed only when transmission and...
  • Page 1417CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Notes: ⋅ These bits can be changed only when transmission and...
  • Page 1418CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.3.9. Serial Chip Select Timing Register: SCSTR3-0 The serial chip select...
  • Page 1419CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit7 to bit0] CSHD7-0: Serial chip select hold delay bits These...
  • Page 1420CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series CSDS CSDS CSDS CSDS CSDS CSDS  Minimum deselect time 15...
  • Page 1421CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.3.10. Serial Chip Select Format Register: SCSFR2-0 The serial chip select...
  • Page 1422CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Serial chip select pin 2 CS2SCINV Serial clock invert bit 0...
  • Page 1423CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Serial chip select pin 2 CS2L3 CS2L2 CSL1 CS2L0 Data length...
  • Page 1424CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series ⋅ Transmission data is output in synchronization with a rising edge...
  • Page 1425CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Serial chip select pin 1 CS1L3 CS1L2 CS1L1 CS1L0 Data length...
  • Page 1426CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series  - SCSFR2n(n=0 to 11) : Address Base addr + 15H...
  • Page 1427CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series ⋅ When this bit is set to "0": Normal synchronous communication....
  • Page 1428CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Notes: ⋅ Settings other than those listed above are prohibited. ⋅...
  • Page 1429CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.3.11. Transfer Byte Register: TBYTE3-0 The transfer byte register (TBYTE) is...
  • Page 1430CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Notes: ⋅ If "00"h is set to these bits, transfer count...
  • Page 1431CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.3.12. Baud rate Generator Register: BGR Baud rate generator register (BGR)...
  • Page 1432CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4. Registers for LIN-UART Registers for LIN-UART is shown. MN705-00010-1v0-E FUJITSU...
  • Page 1433CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.1. Serial Control Register: SCR The serial control register (SCR) allows...
  • Page 1434CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit2 TBIE: ⋅ This bit enables or disables...
  • Page 1435CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.2. Serial Status Register: SSR The serial status register (SSR) allows...
  • Page 1436CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit3 ORE: "0" Read: No overrun error Overrun...
  • Page 1437CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.3. Extended Serial Control Register: ESCR Extended communication control register (ESCR)...
  • Page 1438CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit1, DEL[1:0]: "00": 1-bit length bit0 LIN Break...
  • Page 1439CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.4. Receive Data Register/Transmit Data Register: RDR/TDR The receive data register...
  • Page 1440CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series  Write  TDR1n-0n(n=0 to 11) : Address Base addr +...
  • Page 1441CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.5. Serial Aid Control Status Register: SACSR The serial aid control...
  • Page 1442CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Writing "0" to this bit will reset it to "0". SFD...
  • Page 1443CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit8] TINT: Timer interrupt flag When the serial timer register (STMR)...
  • Page 1444CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit5] TRGE: External trigger enable bit This bit is used to...
  • Page 1445CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit0] TMRE: Serial timer enable bit This bit is used to...
  • Page 1446CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.6. Serial Timer Register: STMR The serial timer register (STMR) is...
  • Page 1447CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.7. Serial Timer Compare Register: STMCR The serial timer compare register...
  • Page 1448CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.8. Sync Field Upper Limit Register: SFUR The Sync Field upper...
  • Page 1449CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.9. Sync Field Lower Limit Register: SFLR The Sync Field lower...
  • Page 1450CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.10. Baud Rate Generator Register: BGR Baud rate generator register (BGR)...
  • Page 1451CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.11. LIN Assist Mode Status Register: LAMSR LIN assist mode status...
  • Page 1452CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit2] LCSC: LIN checksum arithmetic operation completion flag bit This bit...
  • Page 1453CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series LIN automatic header completion flag LAHC Write Read The serial interface...
  • Page 1454CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.12. LIN Assist Mode Control Register: LAMCR LIN assist mode control...
  • Page 1455CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit3] LTDRCL: Transmission data register clear bit This bit clears the...
  • Page 1456CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Notes: ⋅ This function is effective only in the LIN assist...
  • Page 1457CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.13. LIN Assist Mode Interrupt Enable Register: LAMIER LIN assist mode...
  • Page 1458CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit3] LBSERIE: LIN bus error interrupt enable bit This bit enables/disables...
  • Page 1459CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.14. LIN Assist Mode Transmission/Reception ID Register: LAMTID / LAMRID LIN...
  • Page 1460CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.15. LIN Assist Mode Error Status Register: LAMESR LIN assist mode...
  • Page 1461CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Notes: ⋅ Function of this register is effective only in the...
  • Page 1462CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.4.16. LIN Assist Mode Trouble Examination Register: LAMERT LIN assist mode...
  • Page 1463CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit5] Reserved bit This is a reserved bit. The read value...
  • Page 1464CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit2] LSFERT: LIN Sync Field error pseudo trouble setting bit This...
  • Page 1465CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit0] FRET: Framing error pseudo trouble setting bit This bit controls...
  • Page 1466CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.5. Registers for I2C Registers for I2C are shown. MN705-00010-1v0-E FUJITSU...
  • Page 1467CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.5.1. I2C Bus Control Register: IBCR I2C bus control register (IBCR)...
  • Page 1468CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit6 ACT/SCC: This bit differs in meanings between...
  • Page 1469CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit5 ACKE: ⋅ If you set "1" to...
  • Page 1470CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit1 BER: This bit indicates that an error...
  • Page 1471CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit0 (4) When DMA mode is disabled (SSR:DMA=0),...
  • Page 1472CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.5.2. Serial Status Register: SSR Serial status register (SSR) checks for...
  • Page 1473CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit2 RDRF: "0" Read: Receive data register (RDR)...
  • Page 1474CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit1 TDRE: "0" Read: Transmit data register (TDR)...
  • Page 1475CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.5.3. I2C Bus Status Register: IBSR I2C bus status register (IBSR)...
  • Page 1476CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit5 RSA: "0" Read: No reserved address detected...
  • Page 1477CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit3 AL: "0" Read: No arbitration lost occurred...
  • Page 1478CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series Bit name Function bit0 BB: "0" Read: Bus idle state Bus...
  • Page 1479CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.5.4. Receive Data Register/Transmit Data Register: RDR/TDR Receive data register and...
  • Page 1480CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series  Write  - TDR1n-0n(n=3 to 8, 10, 11) : Address...
  • Page 1481CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.5.5. Serial Aid Control Status Register: SACSR The serial aid control...
  • Page 1482CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit7] TINTE: Timer interrupt enable bit This bit is used to...
  • Page 1483CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series [bit0] TMRE: Serial timer enable bit This bit is used to...
  • Page 1484CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.5.6. Serial Timer Register: STMR The serial timer register (STMR) is...
  • Page 1485CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.5.7. Serial Timer Compare Register: STMCR The serial timer compare register...
  • Page 1486CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.5.8. 7-bit Slave Address Mask Register: ISMK 7-bit slave address mask...
  • Page 1487CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.5.9. 7-bit Slave Address Register: ISBA 7-bit slave address register (ISBA)...
  • Page 1488CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 4. Registers MB91520 Series 4.5.10. Baud rate Generator Register: BGR Baud rate generator register (BGR)...
  • Page 1489CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5. Operation of UART This section explains operation of...
  • Page 1490CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.1. Interrupt of UART Interrupt of UART is shown....
  • Page 1491CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.1.1. List of Interrupt of UART The following table...
  • Page 1492CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.1.2. Reception Interrupts and Flag Setting Timing Reception interrupts...
  • Page 1493CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series Notes: When any of following conditions is detected while...
  • Page 1494CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.1.3. Interrupts when Using Reception FIFO and Flag Setting...
  • Page 1495CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series Figure 5-2 Timing of Using FIFO Timing to generate...
  • Page 1496CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.1.4. Transmission Interrupts and Flag Setting Timing Transmission interrupts...
  • Page 1497CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.1.5. Interrupts When Using Transmission FIFO and Flag Setting...
  • Page 1498CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.1.6. Timing of Timer Interrupt Generation and Flag Setting...
  • Page 1499CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2. Operation of UART Operation of UART is shown....
  • Page 1500CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2.1. Transmission/Reception Data Format ⋅ The transmission/reception data always...
  • Page 1501CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series Notes: ⋅ The Figure above shows the example of...
  • Page 1502CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2.2. Transmission Operation ⋅ If the transmission data empty...
  • Page 1503CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2.3. Reception Operation ⋅ When reception operation is enabled...
  • Page 1504CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2.4. Clock Selection ⋅ Internal clocks or external clocks...
  • Page 1505CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2.5. Start Bit Detection ⋅ The start bit is...
  • Page 1506CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2.6. Stop Bit ⋅ You can select 1-4 bit...
  • Page 1507CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2.7. Error Detection ⋅ In operation mode 0, parity...
  • Page 1508CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2.8. Parity Bit ⋅ Parity bit can be added...
  • Page 1509CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2.9. Data Signaling Method ⋅ The INV bit setting...
  • Page 1510CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2.10. Hardware Flow Control When the flow control is...
  • Page 1511CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series ⋅ In case of FIFO used In case of...
  • Page 1512CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2.11. Operation of Serial Timer The serial timer can...
  • Page 1513CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series Note: When the external trigger enable bit (SAGSR:TRGE) is...
  • Page 1514CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series Figure 5-16 Synchronous Transmission Operation (STMCR="10", TBYTE0="2") No data...
  • Page 1515CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series  Transmission Operation by External Trigger If the synchronous...
  • Page 1516CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series If the transmission data register (TDR) has valid transmission...
  • Page 1517CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2.12. Test Mode This section explains the operation of...
  • Page 1518CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.2.13. UART Baud Rate Selection/Setting The UART transmission/reception baud...
  • Page 1519CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series (Example) Bus clock 20MHz, Target baud rate value 153600...
  • Page 1520CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 10/11 ∗ FLmax = (11bit ∗ (V+1) − (V+1)...
  • Page 1521CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series  Reload Values and Errors for Each Internal Clock...
  • Page 1522CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series  External Clock When the EXT bit of the...
  • Page 1523CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.3. Setup Procedure and Program Flow Setup procedure and...
  • Page 1524CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.3.1. Operation Mode 0 (One-to-One Connection) In operation mode...
  • Page 1525CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series FIFO Used (Transmission side) (Reception side) Start Start Operation...
  • Page 1526CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series 5.3.2. Operation Mode 1 (One-to-N Connection) In operation mode...
  • Page 1527CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series  Communication Procedure Communications start when the master CPU...
  • Page 1528CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series Figure 5-23 Example of Flowchart of Master-Slave Communications FIFO...
  • Page 1529CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 5. Operation of UART MB91520 Series FIFO Used (Master CPU) Start (Slave CPU) Start Operation...
  • Page 1530CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6. Operation of CSIO This section explains operation of...
  • Page 1531CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.1. Interrupts of CSIO Interrupts of CSIO are shown....
  • Page 1532CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.1.1. List of Interrupts of CSIO Table 6-1 Interrupt...
  • Page 1533CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.1.2. Reception Interrupts and Flag Setting Timing Reception interrupts...
  • Page 1534CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.1.3. Interrupts when Using Reception FIFO and Flag Setting...
  • Page 1535CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series Figure 6-2 Timing of Interrupts and Flag Setting Timing...
  • Page 1536CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.1.4. Transmission Interrupts and Flag Setting Timing Transmission interrupts...
  • Page 1537CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.1.5. Interrupts When Using Transmission FIFO and Flag Setting...
  • Page 1538CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.1.6. Timing of Timer Interrupt and Flag Setting Timer...
  • Page 1539CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.1.7. Timing of Chip Select Error Generation and Flag...
  • Page 1540CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series Notes: ⋅ When chip select is used, chip select...
  • Page 1541CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.2. Operation of CSIO Operation of CSIO is shown....
  • Page 1542CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.2.1. Normal Transfer (I)  Features Item Description 1...
  • Page 1543CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [1] Master operation (Set SCR:MS=0, SMR:SCKE=1, SCSCR:CSEN3-0="0000"b)  Transmission...
  • Page 1544CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  Successive data transmission or reception wait operation (1)...
  • Page 1545CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [2] Slave operation (Set SCR:MS=1, SMR:SCKE=0, SCSCR:CSEN0=0.)  Transmission...
  • Page 1546CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  Normal Transfer (I) Timing Chart (Serial Chip Select...
  • Page 1547CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [1] Master operation (Set SCR:MS=0, SMR:SCKE=1, SCSCR:CSOE=1, SCSCR:CSENn*=1) *:...
  • Page 1548CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series (3) While operating transmission/reception, the reception data will be...
  • Page 1549CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [2] Slave operation (Set SCR:MS=1, SMR:SCKE=0, SCSCR:CSEN0=1, SCSCR:CSOE=0, SCSCR:SCAM=0)...
  • Page 1550CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.2.2. Normal Transfer (II)  Features Item Description 1...
  • Page 1551CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [1] Master operation (Set SCR:MS=0, SMR:SCKE=1.)  Transmission operation...
  • Page 1552CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  Successive data transmission or reception wait operation (1)...
  • Page 1553CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [2] Slave operation (Set SCR:MS=1, SMR:SCKE=0, SCSCR:CSEN0=0.)  Transmission...
  • Page 1554CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  Normal Transfer (II) Timing Chart (Serial Chip Select...
  • Page 1555CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [1] Master operation (Set SCR:MS=0, SMR:SCKE=1, SCSCR:CSOE=1, SCSCR:CSENn*=1) *:...
  • Page 1556CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series (3) While operating transmission/reception, the reception data will be...
  • Page 1557 CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [2] Slave operation (Set SCR:MS=1, SMR:SCKE=0, SCSCR:CSEN0=1, SCSCR:CSOE=0,...
  • Page 1558CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.2.3. SPI Transfer (I)  Features Item Description 1...
  • Page 1559CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [1] Master operation (Set SCR:MS=0, SMR:SCKE=1, SCSCR:CSEN3-0="0000"b)  Transmission...
  • Page 1560CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  Successive data transmission or reception wait operation (1)...
  • Page 1561CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [2] Slave operation(Set SCR:MS=1, SMR:SCKE=0, SCSCR:CSEN0=0.)  Transmission operation...
  • Page 1562CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  SPI Transfer (I) Timing Chart (Serial Chip Select...
  • Page 1563CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [1] Master operation (Set SCR:MS=0, SMR:SCKE=1, SCSCR:CSOE=1, SCSCR:CSENn*=1) *:"n"...
  • Page 1564CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  Transmission/Reception operation (1) To perform transmission and reception...
  • Page 1565CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [2] Slave operation (Set SCR:MS=1, SMR:SCKE=0, SCSCR:CSEN=1, SCSCR:SCAM=0) ...
  • Page 1566CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.2.4. SPI Transfer (II)  Features Item Description 1...
  • Page 1567CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [1] Master operation (Set SCR:MS=0, SMR:SCKE=1.)  Transmission operation...
  • Page 1568CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  Successive data transmission or reception wait operation (1)...
  • Page 1569CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [2] Slave operation (Set SCR:MS=1, SMR:SCKE=0.)  Transmission operation...
  • Page 1570CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  SPI Transfer (II) Timing Chart (When Serial Chip...
  • Page 1571CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [1] Master operation (Set SCR:MS=0, SMR:SCKE=1, SCSCR:CSOE=1, SCSCR:CSENn*=1) *:...
  • Page 1572CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series (3) Reception data is sampled by the rising edge...
  • Page 1573CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series [2] Slave operation (Set SCR:MS=1, SMR:SCKE=0, SCSCR:CSEN=1, SCSCR:SCAM=0) ...
  • Page 1574CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.2.5. Operation of Serial Timer The serial timer can...
  • Page 1575CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  How to Stop Serial Timer When the serial...
  • Page 1576CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series Figure 6-19 Synchronous Transmission Operation (STMCR="10", TBYTE0="2") No data...
  • Page 1577CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series Notes: ⋅ If the synchronous transmission is enabled (SACSR:TSYNE="1"),...
  • Page 1578CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series Figure 6-20 Transmission Operation by External Trigger (TRG1="0", TRG0="1")...
  • Page 1579CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series Notes: When the transmit data register (TDR) has no...
  • Page 1580CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.2.6. Operation of Serial Chip Select This section explains...
  • Page 1581CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series Notes: ⋅ If the transmission is disabled (SCR:TXE="0") and...
  • Page 1582CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  Timing Adjustment of Serial Chip Select When the...
  • Page 1583CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  Single Operation of Chip select pin (Only Valid...
  • Page 1584CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series See "Operation of Serial Chip Select to Maintain Active...
  • Page 1585CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series Figure 6-29 Round Operation of Chip Select (SST1 and...
  • Page 1586CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  Operation of Serial Chip Select to Maintain Active...
  • Page 1587CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  Format Setting of Serial Chip Select Pin Active...
  • Page 1588CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.2.7. Test Mode This section explains the operation of...
  • Page 1589CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.2.8. Baud Rate Generation The dedicated baud rate generator...
  • Page 1590CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series Notes: ⋅ Set the reload value to "0" to...
  • Page 1591CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series  Reload Counter Functions Reload counters, including transmission and...
  • Page 1592CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series 6.3. Setup Procedure and Program Flow Setup procedure and...
  • Page 1593CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 6. Operation of CSIO MB91520 Series FIFO Used (Master side) (Slave side) Start Start Operating...
  • Page 1594CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7. Operation of LIN Interface (v2.1) This...
  • Page 1595CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.1. Interrupt of LIN Interface (v2.1) manual...
  • Page 1596CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.1.1. List of Interrupts of LIN-UART Interface...
  • Page 1597CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.1.2. Reception Interrupts and Flag Setting Timing...
  • Page 1598CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Timing of LIN break Field Detection...
  • Page 1599CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.1.3. Interrupts when Using Reception FIFO and...
  • Page 1600CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-3 Timing of Interrupt Generation Timing...
  • Page 1601CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.1.4. Transmission Interrupts and Flag Setting Timing...
  • Page 1602CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.1.5. Interrupts When Using Transmission FIFO and...
  • Page 1603CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.1.6. Timer Interrupt and Flag Setting Timing...
  • Page 1604CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.1.7. Sync Field Detection Interrupts and Flag...
  • Page 1605CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.2. Interrupts in LIN Interface (v2.1) Assist...
  • Page 1606CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.2.1. List of Interrupts of LIN-UART Interface...
  • Page 1607CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Interrupt Interrupt Interrupt Flag How to clear...
  • Page 1608CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.2.2. Reception Interrupts and Flag Setting Timing...
  • Page 1609CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series While the overrun error flag is being...
  • Page 1610CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-9 Setting timing of LIN bus...
  • Page 1611CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-10 LIN ID parity error detection...
  • Page 1612CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-11 Setting timing of LIN ID...
  • Page 1613CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  LIN checksum error detection interrupt and...
  • Page 1614CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.2.3. Reception Interrupts and Flag Setting Timing...
  • Page 1615CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.2.4. Transmission Interrupts and Flag Setting Timing...
  • Page 1616CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.2.5. Interrupts and Flag Setting Timing under...
  • Page 1617CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.2.6. Timer Interrupts and Flag Setting Timing...
  • Page 1618CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.2.7. Status Interrupts and Flag Setting Timing...
  • Page 1619CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Automatic Header Completion Interrupt under Reception...
  • Page 1620CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.3. Operation of Serial Timer Operation of...
  • Page 1621CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-18 Start by Sync Field Reception...
  • Page 1622CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Note: When the auto baud rate adjustment...
  • Page 1623CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.4. Test Mode Test mode is shown....
  • Page 1624CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.4.1. Manual Mode  Serial Test Mode...
  • Page 1625CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.4.2. Assist Mode  Serial test mode...
  • Page 1626CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Overview of pseudo LIN bus error...
  • Page 1627CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Overview of pseudo LIN Sync Data...
  • Page 1628CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Note: The transmission/reception processing of the response...
  • Page 1629CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Overview of pseudo framing error test...
  • Page 1630CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.5. Operation of LIN Interface (v2.1) Operation...
  • Page 1631CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.5.1. Manual mode  Master Operations ...
  • Page 1632CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  From Synch Field Transmission to ID...
  • Page 1633CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  From ID Field Transmission to Data...
  • Page 1634CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Master Operation Timing Chart (FIFO Unused)...
  • Page 1635CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Master Device Operation Timing Chart (FIFO...
  • Page 1636CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-33 LIN Bus Timing (at the...
  • Page 1637CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Slave Operations  Selecting Slave Operation...
  • Page 1638CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-34 From LIN Break Field Reception...
  • Page 1639CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  From ID Field Reception to Data...
  • Page 1640CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Slave Operation Timing Chart Figure 7-37...
  • Page 1641CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-38 LIN Bus Timing (DATA Field...
  • Page 1642CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  FIFO Used Figure 7-39 LIN Bus...
  • Page 1643CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-40 LIN Bus Timing (DATA Field...
  • Page 1644CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.5.2. Assist Mode The assist mode has...
  • Page 1645CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series ⋅ When the transmission of ID Field...
  • Page 1646CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  DATA Field transmission/reception Whether DATA Field...
  • Page 1647CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-43 From ID Field transmission to...
  • Page 1648CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-45 From ID Field transmission to...
  • Page 1649CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-47 LIN bus timing (ID register...
  • Page 1650CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-49 LIN bus timing (ID register...
  • Page 1651CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-51 LIN bus timing (ID register...
  • Page 1652CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-52 LIN bus timing (ID register...
  • Page 1653CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Slave operation  Automatic header reception...
  • Page 1654CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 5. When the automatic header reception in...
  • Page 1655CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Notes:  The response transmission data (Data...
  • Page 1656CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Checksum is operated based on LIN...
  • Page 1657CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Notes: ⋅ The noise filter (The serial...
  • Page 1658CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Slave operation timing chart Figure 7-62...
  • Page 1659CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-64 LIN bus timing (DATA Field...
  • Page 1660CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-66 LIN bus timing (DATA Field...
  • Page 1661CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-68 LIN bus timing (DATA Field...
  • Page 1662CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.5.3. LIN-UART Baud Rate Selection/Setting The LIN-UART...
  • Page 1663CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.6. Setup Procedure and Program Flow Setup...
  • Page 1664CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.6.1. Manual mode The example of the...
  • Page 1665CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-72 Example of a Flowchart in...
  • Page 1666CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Slave operation Figure 7-73 Example of...
  • Page 1667CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-74 Example of a Flowchart in...
  • Page 1668CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series 7.6.2. Assist mode The example of the...
  • Page 1669CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Flowchart Example  Master operation Figure...
  • Page 1670CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-76 Example of a Flowchart in...
  • Page 1671CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series  Slave operation Figure 7-77 Example of...
  • Page 1672CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 7. Operation of LIN Interface (v2.1) MB91520 Series Figure 7-78 Example of a Flowchart in...
  • Page 1673CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8. Operation of I2C This section is explains operation...
  • Page 1674CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.1. Interrupts of I2C Interrupts of I2C is shown....
  • Page 1675CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Interrupt Interrupt Interrupt Flag Clearing of interrupt request request...
  • Page 1676CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.1.2. Timing of Timer Interrupt Generation and Flag Setting...
  • Page 1677CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.2. Operation for I2C Interface Communication Operation for I2C...
  • Page 1678CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.2.4. I2C Bus Error If a stop condition or...
  • Page 1679CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.2.5. Serial Timer Operations Serial timer can be used...
  • Page 1680CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Note: When external trigger enable bit (SAGSR:TRGE) is "1"...
  • Page 1681CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.2.6. Baud Rate Generation The dedicated baud rate generator...
  • Page 1682CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series  Reload Values Relating to Baud Rates and Internal...
  • Page 1683CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.3. I2C Master Mode I2C master mode is shown....
  • Page 1684CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Note: Bus clock should be used at 8MHz or...
  • Page 1685CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.3.2. Slave Address Output When a start condition is...
  • Page 1686CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Address and Data Direction (when Transmission/Reception FIFO is Enabled)...
  • Page 1687CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.3.3. Acknowledge Reception by Transmitting First Byte When the...
  • Page 1688CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Table 8-4 Operation after Acknowledge Reception (when DMA mode...
  • Page 1689CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series  DMA Mode Disabled (SSR:DMA=0)  FIFO Disabled (Both...
  • Page 1690CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series  DMA Mode Enabled (SSR:DMA=1)  FIFO Disabled (Both...
  • Page 1691CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-10 Acknowledge (FIFO Disable, IBSR:RSA="0", and the Response...
  • Page 1692CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-12 Acknowledge (FIFO Disable, IBSR:RSA="1", and the Response...
  • Page 1693CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-14 Acknowledge (If FIFO Is Enabled, Transmission FIFO...
  • Page 1694CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.3.4. Data Transmission by Master If the data direction...
  • Page 1695CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series  Data transmission to slave when DMA mode is...
  • Page 1696CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series  Data transmission to slave when DMA mode is...
  • Page 1697CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series *1: If any of following conditions is met, it...
  • Page 1698CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-15 Master Transmission Interrupt (1)-when FIFO is Disabled...
  • Page 1699CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-17 Master Transmission Interrupt (3)-when FIFO is Disabled...
  • Page 1700CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-19 Master Transmission Interrupt (5)-when FIFO is Disabled...
  • Page 1701CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-21 Master Transmission Interrupt (7)-when FIFO is Enabled...
  • Page 1702CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-23 Master Transmission Interrupt (9)-when FIFO is Enabled...
  • Page 1703CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-25 Master Transmission Interrupt (11)-when FIFO is Disabled...
  • Page 1704CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-27 Master Transmission Interrupt (13)-when FIFO is Disabled...
  • Page 1705CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-29 Master Transmission Interrupt (15)-when FIFO is Disabled...
  • Page 1706CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-31 Master Transmission Interrupt (17)-when FIFO is Enabled...
  • Page 1707CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.3.5. Data Reception by Master  When DMA mode...
  • Page 1708CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series ⋅ If the send/receive FIFO operation is enabled. (1)...
  • Page 1709CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series The following gives an example of procedure to receive...
  • Page 1710CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series ⋅ When the master device is receiving data and...
  • Page 1711CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-35 Master Reception interrupt (3)-when FIFO is Enabled...
  • Page 1712CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-38 Master Reception interrupt (2)-when FIFO is Disabled...
  • Page 1713CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.3.6. Arbitration Lost If data of the master device...
  • Page 1714CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.3.8. Repetition Start Condition Issue when DMA Mode Enabled...
  • Page 1715CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.4. I2C Slave Mode I2C slave mode is shown....
  • Page 1716CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.4.1. Detection of Slave Address Matching When the (repeated)...
  • Page 1717CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series ⋅ Reserved address detected If the first byte already...
  • Page 1718CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series  When DMA mode is enable (SSR:DMA=1) ⋅ If...
  • Page 1719CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-43 Slave Reception Interrupt (2)-when FIFO is Disabled...
  • Page 1720CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-46 Slave Reception Interrupt (5)-when FIFO is Enabled...
  • Page 1721CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-48 Slave Reception Interrupt (7)-when FIFO is Disabled...
  • Page 1722CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-50 Slave Reception Interrupt (9)-when FIFO is Disabled...
  • Page 1723CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-52 Slave Reception Interrupt (11)-when FIFO is Enabled...
  • Page 1724CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.4.4. Slave Mode Transmission If the slave address matches...
  • Page 1725CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series 8.5. Example of I2C Flowchart Example of I2C flowchart...
  • Page 1726CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-55 Example of I2C Flowchart (FIFO Memory Not...
  • Page 1727CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-56 Example of I2C Flowchart (FIFO Memory Not...
  • Page 1728CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-57 Example of I2C Flowchart (FIFO Memory Not...
  • Page 1729CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-58 Example of I2C Flowchart (FIFO Memory Not...
  • Page 1730CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-59 Example of I2C Flowchart (FIFO Memory Not...
  • Page 1731CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series Figure 8-60 Example of I2C Flowchart (FIFO Memory Not...
  • Page 1732CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE 8. Operation of I2C MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 1694 CHAPTER : MULTI-FUNCTION SERIAL...
  • Page 1733: CHAPTER 41: CANCHAPTER 41: CAN 1. Overview MB91520 Series CHAPTER : CAN This chapter explains the CAN. 1. Overview 2. Features 3....
  • Page 1734CHAPTER 41: CAN 1. Overview MB91520 Series 1. Overview This section explains the overview of the CAN. This series includes...
  • Page 1735CHAPTER 41: CAN 2. Features MB91520 Series 2. Features This section explains the features of the CAN. The CAN of...
  • Page 1736CHAPTER 41: CAN 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the CAN. A block diagram...
  • Page 1737CHAPTER 41: CAN 4. Registers MB91520 Series 4. Registers This section explains the registers of the CAN. MN705-00010-1v0-E FUJITSU SEMICONDUCTOR...
  • Page 1738CHAPTER 41: CAN 4. Registers MB91520 Series 4.1. Overview This section shows the overview of the registers. The CAN includes...
  • Page 1739CHAPTER 41: CAN 4. Registers MB91520 Series 4.1.1. List of Base-addresses (Base-addr), External Pins and Buffer Size This section shows...
  • Page 1740CHAPTER 41: CAN 4. Registers MB91520 Series 4.1.2. List of Overall Control Register This section shows the list of overall...
  • Page 1741CHAPTER 41: CAN 4. Registers MB91520 Series 4.1.3. List of Message Interface Register This section shows the list of message...
  • Page 1742CHAPTER 41: CAN 4. Registers MB91520 Series Registers Address Note +0 +1 +2 +3 IF1 data B register 1 IF1...
  • Page 1743CHAPTER 41: CAN 4. Registers MB91520 Series Registers Address Note +0 +1 +2 +3 IF2 message control register Reserved bits...
  • Page 1744CHAPTER 41: CAN 4. Registers MB91520 Series 4.1.4. List of Message Handler Register This section shows the list of message...
  • Page 1745CHAPTER 41: CAN 4. Registers MB91520 Series Registers Address Note +0 +1 +2 +3 CAN interrupt pending register 2 CAN...
  • Page 1746CHAPTER 41: CAN 4. Registers MB91520 Series 4.2. Overall Control Registers Overall control registers are shown. Overall control registers control...
  • Page 1747CHAPTER 41: CAN 4. Registers MB91520 Series 4.2.1. CAN Control Register : CTRLR The bit configuration of the CAN control...
  • Page 1748CHAPTER 41: CAN 4. Registers MB91520 Series [bit5]: Automatic retransmission disable bit The CAN controller retransmits the frame automatically when...
  • Page 1749CHAPTER 41: CAN 4. Registers MB91520 Series [bit2]: Status interrupt code enable bit SIE Function Disables the interrupt code setting...
  • Page 1750CHAPTER 41: CAN 4. Registers MB91520 Series 4.2.2. CAN Status Register : STATR The bit configuration of the CAN status...
  • Page 1751CHAPTER 41: CAN 4. Registers MB91520 Series [bit4]: Successful message reception bit RxOk Function Indicates successful message communication is not...
  • Page 1752CHAPTER 41: CAN 4. Registers MB91520 Series Notes: ⋅ The status interrupt code (8000H) is set to the CAN interrupt...
  • Page 1753CHAPTER 41: CAN 4. Registers MB91520 Series 4.2.3. CAN Error Counter : ERRCNT The bit configuration of the CAN error...
  • Page 1754CHAPTER 41: CAN 4. Registers MB91520 Series 4.2.4. CAN Bit Timing Register : BTR The bit configuration of the CAN...
  • Page 1755CHAPTER 41: CAN 4. Registers MB91520 Series 4.2.5. CAN Interrupt Register : INTR The bit configuration of the CAN interrupt...
  • Page 1756CHAPTER 41: CAN 4. Registers MB91520 Series 4.2.6. CAN Test Register : TESTR The bit configuration of the CAN test...
  • Page 1757CHAPTER 41: CAN 4. Registers MB91520 Series [bit4] LBack : Loopback Mode LBack Function 0 Disables loopback mode. [Initial value]...
  • Page 1758CHAPTER 41: CAN 4. Registers MB91520 Series 4.2.7. CAN Prescaler Extension Register : BRPER The bit configuration of the CAN...
  • Page 1759CHAPTER 41: CAN 4. Registers MB91520 Series 4.3. Message Interface Register This section shows the message interface register. Provides two...
  • Page 1760CHAPTER 41: CAN 4. Registers MB91520 Series 4.3.1. IFx Command Request Register : IFxCREQ The bit configuration of the IFx...
  • Page 1761CHAPTER 41: CAN 4. Registers MB91520 Series (2) Test basic mode IF1 command request register BUSY Function 0 Disables the...
  • Page 1762CHAPTER 41: CAN 4. Registers MB91520 Series 4.3.2. IFx Command Mask Register (IFxCMSK) The bit configuration of the IFx command...
  • Page 1763CHAPTER 41: CAN 4. Registers MB91520 Series (1) When the transfer direction is write (WR/RD="1") [bit6] Mask : Mask data...
  • Page 1764CHAPTER 41: CAN 4. Registers MB91520 Series [bit0] Data B : Data 4 to 7 update bit Data B Function...
  • Page 1765CHAPTER 41: CAN 4. Registers MB91520 Series [bit2] TxRqst/NewDat : Data update bit TxRqst/ Function NewDat Indicates holding the NewDat...
  • Page 1766CHAPTER 41: CAN 4. Registers MB91520 Series 4.3.3. IFx Mask Registers 1, 2 : IFxMSK1, IFxMSK2 The bit configuration of...
  • Page 1767CHAPTER 41: CAN 4. Registers MB91520 Series 4.3.4. IFx Arbitration Registers 1, 2 : IFxARB1, IFxARB2 The bit configuration of...
  • Page 1768CHAPTER 41: CAN 4. Registers MB91520 Series 4.3.5. IFx Message Control Register : IFxMCTR The bit configuration of the IFx...
  • Page 1769CHAPTER 41: CAN 4. Registers MB91520 Series 4.3.6. IFx Data Registers A1, A2, B1, B2 : IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2...
  • Page 1770CHAPTER 41: CAN 4. Registers MB91520 Series 4.4. Message Object This section shows the message object. The message RAM has...
  • Page 1771CHAPTER 41: CAN 4. Registers MB91520 Series 4.4.1. Configuration of Message Object The configuration of the message object is shown....
  • Page 1772CHAPTER 41: CAN 4. Registers MB91520 Series 4.4.2. Functions of Message Object The functions of the message object are shown....
  • Page 1773CHAPTER 41: CAN 4. Registers MB91520 Series ID28 to ID0: Message ID ID Function ID28 to ID0 Instructs a 29-bit...
  • Page 1774CHAPTER 41: CAN 4. Registers MB91520 Series MDir: Message direction mask bit MDir Function 0 Masks the message direction bit...
  • Page 1775CHAPTER 41: CAN 4. Registers MB91520 Series TxIE: Transmission interrupt flag enable bit TxIE Function 0 The IntPnd remains unchanged...
  • Page 1776CHAPTER 41: CAN 4. Registers MB91520 Series Note: The received DLC will be stored in the DLC bit when the...
  • Page 1777CHAPTER 41: CAN 4. Registers MB91520 Series 4.5. Message Handler Registers Message handler registers are shown. All message handler registers...
  • Page 1778CHAPTER 41: CAN 4. Registers MB91520 Series 4.5.1. CAN Transmission Request Registers : TREQR1 to TREQR4 The bit configuration of...
  • Page 1779CHAPTER 41: CAN 4. Registers MB91520 Series  CAN Transmission Request Register 2 (upper byte): Address Base + 80H (Access:...
  • Page 1780CHAPTER 41: CAN 4. Registers MB91520 Series Set/reset conditions of the TxRqst bits are shown below. Set condition It is...
  • Page 1781CHAPTER 41: CAN 4. Registers MB91520 Series 4.5.2. CAN Data Update Registers : NEWDT1 to NEWDT4 The bit configuration of...
  • Page 1782CHAPTER 41: CAN 4. Registers MB91520 Series  CAN Data Update Register 2 (upper byte): Address Base + 90H (Access:...
  • Page 1783CHAPTER 41: CAN 4. Registers MB91520 Series Set/reset conditions of the NewDat bits are shown below. Set condition When the...
  • Page 1784CHAPTER 41: CAN 4. Registers MB91520 Series 4.5.3. CAN Interrupt Pending Registers :INTPND1 to INTPND4 The bit configuration of the...
  • Page 1785CHAPTER 41: CAN 4. Registers MB91520 Series  CAN Interrupt Pending Register 2 (upper byte): Address Base + A0H (Access:...
  • Page 1786CHAPTER 41: CAN 4. Registers MB91520 Series Set/reset conditions of the IntPnd bits are shown below. Set condition If the...
  • Page 1787CHAPTER 41: CAN 4. Registers MB91520 Series 4.5.4. CAN Message Valid Registers : MSGVAL1 to MSGVAL4 The bit configuration of...
  • Page 1788CHAPTER 41: CAN 4. Registers MB91520 Series  CAN Message Valid Register 2 (upper byte): Address Base + B0H (Access:...
  • Page 1789CHAPTER 41: CAN 4. Registers MB91520 Series Set/reset conditions of the MsgVal bits are shown below. Set condition When the...
  • Page 1790CHAPTER 41: CAN 5. Operation MB91520 Series 5. Operation This section explains the operation of the CAN. The CAN has...
  • Page 1791CHAPTER 41: CAN 5. Operation MB91520 Series 5.1. Message Object The message object is shown. This section explains the message...
  • Page 1792CHAPTER 41: CAN 5. Operation MB91520 Series 5.1.1. Message Object Message object is shown. Message object settings (excluding MsgVal, NewDat,...
  • Page 1793CHAPTER 41: CAN 5. Operation MB91520 Series 5.1.2. Data Transmission/Reception with Message RAM Data transmission/reception with message RAM is shown....
  • Page 1794CHAPTER 41: CAN 5. Operation MB91520 Series 5.2. Message Transmission Operation Message transmission operation is shown. This section explains the...
  • Page 1795CHAPTER 41: CAN 5. Operation MB91520 Series 5.2.1. Message Transmission Message transmission is shown. If there is no data transfer...
  • Page 1796CHAPTER 41: CAN 5. Operation MB91520 Series 5.2.2. Transmission Priority Transmission priority is shown. Transmission priority of a message object...
  • Page 1797CHAPTER 41: CAN 5. Operation MB91520 Series 5.2.3. Transmission Message Object Setting Transmission message object setting is shown. The initialization...
  • Page 1798CHAPTER 41: CAN 5. Operation MB91520 Series 5.2.4. Update of Transmission Message Object Update of transmission message object is shown....
  • Page 1799CHAPTER 41: CAN 5. Operation MB91520 Series 5.3. Message Reception Operation Message reception operation is shown. This section explains the...
  • Page 1800CHAPTER 41: CAN 5. Operation MB91520 Series 5.3.1. Reception Message Acceptance Filter Reception message acceptance filter is shown. When the...
  • Page 1801CHAPTER 41: CAN 5. Operation MB91520 Series 5.3.2. Reception Priority Reception priority is shown. Reception priority of a message object...
  • Page 1802CHAPTER 41: CAN 5. Operation MB91520 Series 5.3.3. Data Frame Reception Data frame reception is shown. CAN controller transfers and...
  • Page 1803CHAPTER 41: CAN 5. Operation MB91520 Series 5.3.4. Remote Frame Remote frame is shown. The following three processes are performed...
  • Page 1804CHAPTER 41: CAN 5. Operation MB91520 Series 5.3.5. Reception Message Object Setting Reception message object setting is shown. The initialization...
  • Page 1805CHAPTER 41: CAN 5. Operation MB91520 Series 5.3.6. Reception Message Processing Reception message processing is shown. CPU can read reception...
  • Page 1806CHAPTER 41: CAN 5. Operation MB91520 Series 5.4. FIFO Buffer Function FIFO buffer function is shown. This section explains the...
  • Page 1807CHAPTER 41: CAN 5. Operation MB91520 Series 5.4.1. Configuration of FIFO Buffer The configuration of FIFO buffer is shown. The...
  • Page 1808CHAPTER 41: CAN 5. Operation MB91520 Series 5.4.2. Message Reception by FIFO Buffer Message reception by FIFO buffer is shown....
  • Page 1809CHAPTER 41: CAN 5. Operation MB91520 Series 5.4.3. Reading from FIFO Buffer Reading from FIFO buffer is shown. CPU can...
  • Page 1810CHAPTER 41: CAN 5. Operation MB91520 Series Figure 5-2 CPU Processing of FIFO Buffer Start Message interrupt Reading the CAN...
  • Page 1811CHAPTER 41: CAN 5. Operation MB91520 Series 5.5. Interrupt Function Interrupt function is shown. This section explains the processing of...
  • Page 1812CHAPTER 41: CAN 5. Operation MB91520 Series 5.6. Bit Timing and CAN System Clock (fsys) Generation Bit timing and CAN...
  • Page 1813CHAPTER 41: CAN 5. Operation MB91520 Series Table 5-3 CAN Bit Time Parameters Parameter Range Function BRP [1 to 32]...
  • Page 1814CHAPTER 41: CAN 5. Operation MB91520 Series Table 5-4 CAN Controller Parameters Parameter Range Function Defines the time quantity tq....
  • Page 1815CHAPTER 41: CAN 5. Operation MB91520 Series 5.7. Test Mode Test mode is shown. This section explains the test mode...
  • Page 1816CHAPTER 41: CAN 5. Operation MB91520 Series 5.7.1. Test Mode Setting Test mode setting is shown. The CAN controller enters...
  • Page 1817CHAPTER 41: CAN 5. Operation MB91520 Series 5.7.2. Silent Mode Silent mode is shown. The CAN controller enters silent mode...
  • Page 1818CHAPTER 41: CAN 5. Operation MB91520 Series 5.7.3. Loopback Mode Loopback mode is shown. The CAN controller enters loopback mode...
  • Page 1819CHAPTER 41: CAN 5. Operation MB91520 Series 5.7.4. Combination of Silent and Loopback Modes Combination of silent and loopback modes...
  • Page 1820CHAPTER 41: CAN 5. Operation MB91520 Series 5.7.5. Basic Mode Basic mode is shown. The CAN controller enters basic mode...
  • Page 1821CHAPTER 41: CAN 5. Operation MB91520 Series 5.7.6. Software Control of the CAN_TX Pin Software control of the CAN_TX pin...
  • Page 1822CHAPTER 41: CAN 5. Operation MB91520 Series 5.8. Software Initialization Software initialization is shown. Software-controlled initialization is as follows: The...
  • Page 1823CHAPTER 41: CAN 5. Operation MB91520 Series 5.9. CAN Wake Up Function CAN Wake Up function is shown. It can...
  • Page 1824CHAPTER 41: CAN 5. Operation MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 1786 CHAPTER : CAN FUJITSU SEMICONDUCTOR CONFIDENTIAL 93
  • Page 1825: CHAPTER 42: CAN clock prescalerCHAPTER 42: CAN CLOCK PRESCALER 1. Overview MB91520 Series CHAPTER : CAN clock prescaler This chapter explains the CAN clock...
  • Page 1826CHAPTER 42: CAN CLOCK PRESCALER 1. Overview MB91520 Series 1. Overview This section gives an overview of the CAN clock...
  • Page 1827CHAPTER 42: CAN CLOCK PRESCALER 2. Features MB91520 Series 2. Features This section explains features of the CAN clock prescaler....
  • Page 1828CHAPTER 42: CAN CLOCK PRESCALER 3. Configuration MB91520 Series 3. Configuration This section shows configuration of the CAN clock prescaler....
  • Page 1829CHAPTER 42: CAN CLOCK PRESCALER 4. Registers MB91520 Series 4. Registers This section shows registers of the CAN clock prescaler....
  • Page 1830CHAPTER 42: CAN CLOCK PRESCALER 4. Registers MB91520 Series 4.1. CAN Prescaler Register : CANPRE The bit configuration of CAN...
  • Page 1831CHAPTER 42: CAN CLOCK PRESCALER 4. Registers MB91520 Series Input CAN Input CAN Input CAN CANPRE prescaler prescaler prescaler Function...
  • Page 1832CHAPTER 42: CAN CLOCK PRESCALER 4. Registers MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 1794 CHAPTER : CAN clock prescaler FUJITSU...
  • Page 1833: CHAPTER 43: D/A CONVERTERCHAPTER 43: D/A CONVERTER 1. Overview MB91520 Series CHAPTER : D/A CONVERTER This chapter explains the D/A converter. 1. Overview...
  • Page 1834CHAPTER 43: D/A CONVERTER 1. Overview MB91520 Series 1. Overview This section explains the overview of the D/A converter. The...
  • Page 1835CHAPTER 43: D/A CONVERTER 2. Features MB91520 Series 2. Features This section explains the features of the D/A converter. ...
  • Page 1836CHAPTER 43: D/A CONVERTER 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the D/A converter. Figure...
  • Page 1837CHAPTER 43: D/A CONVERTER 4. Registers MB91520 Series 4. Registers This section explains the registers of the D/A converter. ...
  • Page 1838CHAPTER 43: D/A CONVERTER 4. Registers MB91520 Series 4.1. DA Control Register : DACR The bit configuration of the DA...
  • Page 1839CHAPTER 43: D/A CONVERTER 4. Registers MB91520 Series 4.2. DA Data Register : DADR The bit configuration of the DA...
  • Page 1840CHAPTER 43: D/A CONVERTER 5. Operation MB91520 Series 5. Operation The section explains the operation of the D/A converter. The...
  • Page 1841CHAPTER 43: D/A CONVERTER 6. Note MB91520 Series 6. Note The section explains the notes about the D/A converter. The...
  • Page 1842CHAPTER 43: D/A CONVERTER 6. Note MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 1804 CHAPTER : D/A CONVERTER FUJITSU SEMICONDUCTOR CONFIDENTIAL...
  • Page 1843: CHAPTER 44: 12-BIT A/D CONVERTERCHAPTER 44: 12-BIT A/D CONVERTER 1. Overview MB91520 Series CHAPTER : 12-BIT A/D CONVERTER This chapter explains the 12-bit A/D...
  • Page 1844CHAPTER 44: 12-BIT A/D CONVERTER 1. Overview MB91520 Series 1. Overview This section explains the overview of the 12-bit A/D...
  • Page 1845CHAPTER 44: 12-BIT A/D CONVERTER 2. Features MB91520 Series 2. Features This section explains features of the 12-bit A/D converter....
  • Page 1846CHAPTER 44: 12-BIT A/D CONVERTER 2. Features MB91520 Series 2.1. Function of A/D Activation Compare The function of A/D activation...
  • Page 1847CHAPTER 44: 12-BIT A/D CONVERTER 2. Features MB91520 Series  A/D conversion data  When A/D conversion completions, conversion-result data...
  • Page 1848CHAPTER 44: 12-BIT A/D CONVERTER 2. Features MB91520 Series 2.2. Function of A/D Activation Arbitration The function of A/D activation...
  • Page 1849CHAPTER 44: 12-BIT A/D CONVERTER 2. Features MB91520 Series 2.3. Functions of 12-bit A/D Converter Control The function of 12-bit...
  • Page 1850CHAPTER 44: 12-BIT A/D CONVERTER 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the 12-bit A/D...
  • Page 1851CHAPTER 44: 12-BIT A/D CONVERTER 3. Configuration MB91520 Series  Configuration of A/D Activation Arbitration Figure 3-2 Configuration of A/D...
  • Page 1852CHAPTER 44: 12-BIT A/D CONVERTER 3. Configuration MB91520 Series  Configuration of 12-bit A/D Converter Control Figure 3-3 Configuration of...
  • Page 1853CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4. Registers This section explains registers of the 12-bit A/D converter....
  • Page 1854CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Registers Address +0 +1 +2 +3 Compare buffer register 18 (ADCOMPB18)...
  • Page 1855CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Registers Address +0 +1 +2 +3 A/D activation trigger control status...
  • Page 1856CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Registers Address +0 +1 +2 +3 A/D activation trigger extend control...
  • Page 1857CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Registers Address +0 +1 +2 +3 Range compare control Range compare...
  • Page 1858CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Registers Address +0 +1 +2 +3 A/D software activation 0x1470 Reserved...
  • Page 1859CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Registers Address +0 +1 +2 +3 0x14D8 to Reserved Reserved 0x14F4...
  • Page 1860CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Registers Address +0 +1 +2 +3 Upper bound threshold setting register...
  • Page 1861CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series  List of 12-bit A/D Converter Control Registers Table 4-3 List...
  • Page 1862CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.1. Register of Analog Input Control The register of the analog...
  • Page 1863CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.1.1. Analog Input Enable Register : ADER The bit configuration of...
  • Page 1864CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series  ADERL1: Address 04B2H (Access: Byte, Half-word) bit15 bit14 bit13 bit12...
  • Page 1865CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2. Register of A/D Activation Compare The registers of the A/D...
  • Page 1866CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.1. A/D Software Activation Register: ADTSS0, ADTSS1 The bit configuration of...
  • Page 1867CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.2. A/D Software Activation Channel Select Register : ADTSE0, ADTSE1 The...
  • Page 1868CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series  ADTSE1: Address 1474H (Access: Byte, Half-word, Word) bit31 bit30 bit29...
  • Page 1869CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.3. Compare Buffer Register / Compare Register : ADCOMPB0 to ADCOMPB47...
  • Page 1870CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series  ADCOMP0 to ADCOMP31: Address 130CH to 134AH (Access: Half-word, Word)...
  • Page 1871CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.4. A/D Activation Trigger Control Status Register : ADTCS0 to ADTCS47...
  • Page 1872CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series [bit14] INT : Interrupt request flag bit Function INT Read Write...
  • Page 1873CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Notes:  Since the activation factor select bit changes immediately when...
  • Page 1874CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Note: Please set the A/D data register protection clear select bit...
  • Page 1875CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Note: Please confirm the 16-bit free-run timer has stopped whenever the...
  • Page 1876CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.5. A/D Data Register : ADTCD0 to ADTCD47 The bit configuration...
  • Page 1877CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series [bit13,bit12] Reserved These bits must always be written to "0". [bit11,...
  • Page 1878CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.6. A/D Activation Trigger Extend Control Register : ADTECS0 to ADTECS47...
  • Page 1879CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series [bit4 to bit0] CHSEL4 to CHSEL0 : Analog channel select bit...
  • Page 1880CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series  ADTECS32 to ADTECS47: Address 1538H to 1556H (Access: Byte, Half-word,...
  • Page 1881CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.7. Upper Bound Threshold Setting Register : ADRCUT0 to ADRCUT7 The...
  • Page 1882CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.8. Lower Bound Threshold Setting Register : ADRCLT0 to ADRCLT7 The...
  • Page 1883CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.9. Range Compare Control Status Register: ADRCCS0 to ADRCCS47 The bit...
  • Page 1884CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Notes:  Please do not set "000B" to the continuous detection...
  • Page 1885CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series [bit1,bit0] RCOTS1, RCOTS0 : Upper and lower bound threshold select bit...
  • Page 1886CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.10. Range Compare Threshold Over Flag Register : ADRCOT0, ADRCOT1 The...
  • Page 1887CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series  When inside the range is confirmed, the threshold over flag...
  • Page 1888CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.11. Range Compare Flag Register : ADRCIF0, ADRCIF1 The bit configuration...
  • Page 1889CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Notes:  If the read-modify-write (RMW) instruction is executed, "1" will...
  • Page 1890CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series  ADRCIF1: Address 15ACH (Access: Byte, Half-word, Word) bit31 bit30 bit29...
  • Page 1891CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.12. Scan Conversion Control Status Register : ADSCANS0, ADSCANS1 The bit...
  • Page 1892CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series [bit5] SCMD : Continuousness and stop scan conversion mode select bit...
  • Page 1893CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.13. Activation Channel Conversion Count Setting Register : ADNCS0 to ADNCS23...
  • Page 1894CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Note: Please do not change the conversion count specification bit while...
  • Page 1895CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.14. Data Protection Status Flag Register : ADPRTF0, ADPRTF1 The bit...
  • Page 1896CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series  ADPRTF1: Address 15C4H (Access: Byte, Half-word, Word) bit31 bit30 bit29...
  • Page 1897CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.2.15. Activation Channel Conversion Completion Flag Register : ADEOCF0, ADEOCF1 The...
  • Page 1898CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series  ADEOCF1: Address 15C8H (Access: Byte, Half-word, Word) bit31 bit30 bit29...
  • Page 1899CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.3. Register of 12-BIT A/D Converter Control The registers of the...
  • Page 1900CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.3.1. A/D Control Status Register: ADCS0, ADCS1 The bit configuration of...
  • Page 1901CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.3.2. A/D Channel Status Register : ADCH The bit configuration of...
  • Page 1902CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.3.3. A/D Mode Setting Register : ADMD The bit configuration of...
  • Page 1903CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Recommended setting Peripheral clock CT1 CT0 Compare time (ns) (MHz) 40...
  • Page 1904CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Recommended setting (Use conditions: AVCC=4.5V to 5.5V) Peripheral clock ST1 ST0...
  • Page 1905CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series 4.3.4. A/D Sampling Time Setting Per Channel Register : ADSTPCS The...
  • Page 1906CHAPTER 44: 12-BIT A/D CONVERTER 4. Registers MB91520 Series Table 4-4 For sampling time setting and analog channel each channels...
  • Page 1907CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5. Operation This section explains operation. MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 1869...
  • Page 1908CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.1. Interrupt of A/D activation compare This section shows the interrupt...
  • Page 1909CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.1.1. A/D conversion completion interrupt The A/D conversion completion interrupt is...
  • Page 1910CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.1.2. Scan conversion completion interrupt by conversion count specification The scan...
  • Page 1911CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.1.3. Range comparison interrupt The range comparison interrupt is explained. Table...
  • Page 1912CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2. A/D activation compare operation This section explains the A/D activation...
  • Page 1913CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.1. A/D activation The A/D activation is explained. The activation is...
  • Page 1914CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.2. A/D activation enable The A/D activation enable is explained. The...
  • Page 1915CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.3. Free-run timer input The free-run timer input is explained. The...
  • Page 1916CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.4. Analog channel select The analog channel select is explained. An...
  • Page 1917CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.5. Software activation The software activation is explained. The A/D activation...
  • Page 1918CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.6. External trigger activation The external trigger activation is explained. The...
  • Page 1919CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.7. Reload timer activation The reload timer activation is explained. The...
  • Page 1920CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.8. Compare match activation The compare match activation is explained. The...
  • Page 1921CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series  SEL1, SEL0=10B: Compare match activation when only counting down Figure...
  • Page 1922CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series  About the setting of the compare value of the compare...
  • Page 1923CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series  Compare register buffer function of compare match activation If "0"...
  • Page 1924CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series Figure 5-8 When 16-bit free-run timer counting up, the compare register...
  • Page 1925CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series Figure 5-10 When 16-bit free-run timer counting up and down, the...
  • Page 1926CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.9. PPG activation The PPG activation is explained. The A/D activation...
  • Page 1927CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.10. Activation request mode The activation request mode is explained. The...
  • Page 1928CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.11. A/D conversion data The A/D conversion data is explained. The...
  • Page 1929CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.12. Protection function The protection function is explained. Each A/D data...
  • Page 1930CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.13. Scan conversion mode The scan conversion mode is explained. The...
  • Page 1931CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series Note: When the data protection function is effective (ADTCS.PRT="1") and it...
  • Page 1932CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series  In case of data protection function invalid (ADTCS.PRT="0") The A/D...
  • Page 1933CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series Figure 5-16 Continuous scan conversion when conversion count of each channel...
  • Page 1934CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series converted in the activation channel is stored.  In case of...
  • Page 1935CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series Figure 5-18 Stop scan conversion when conversion count of each channel...
  • Page 1936CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.14. High priority activation request operation of other activation channel during...
  • Page 1937CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series Figure 5-20 Operation of high priority activation factor request by other...
  • Page 1938CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.15. Forced termination of activation request The forced termination of activation...
  • Page 1939CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.2.16. Range comparison function The range comparison function is explained. ...
  • Page 1940CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series  Range comparison operation When the range comparison enable setting (ADRCCS.RCOE="1"),...
  • Page 1941CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series Table 5-9 Continuous detecting function operation condition ⋅ Each activation channel...
  • Page 1942CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series  Example of operating range comparison Table 5-11 Range comparison upper...
  • Page 1943CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 10. Because the range comparison result continuously reached the continuous detection...
  • Page 1944CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.3. A/D Activation Arbitration Operation This section explains the A/D activation...
  • Page 1945CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.3.1. A/D Activation Trigger Arbitration The A/D activation trigger arbitration is...
  • Page 1946CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.3.2. Analog Channel Select The analog channel select is explained. The...
  • Page 1947CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.3.3. A/D Conversion Cancel Function The A/D conversion cancel function is...
  • Page 1948CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.4. 12-bit A/D Converter Operation This section explains the 12-bit A/D...
  • Page 1949CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.4.1. Operation Timing The operation timing is shown. Figure 5-23 12-bit...
  • Page 1950CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.4.2. Activation Factors The activation factor is shown. AD conversion activation...
  • Page 1951CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.4.3. A/D Conversion The A/D conversion is shown. One sequence of...
  • Page 1952CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.4.4. Re-activation The re-activation is shown. When an activation trigger signal...
  • Page 1953CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.4.5. A/D Conversion Cancel The A/D conversion cancel is shown. If...
  • Page 1954CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.4.6. Analog Channel Select Control The analog channel select control is...
  • Page 1955CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.4.7. A/D Conversion Time The A/D conversion time is shown. The...
  • Page 1956CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.4.8. A/D Conversion Completion and A/D Data Retrieval The A/D conversion...
  • Page 1957CHAPTER 44: 12-BIT A/D CONVERTER 5. Operation MB91520 Series 5.4.9. Power down The power down is shown. Power down is...
  • Page 1958CHAPTER 44: 12-BIT A/D CONVERTER 6. Notes MB91520 Series 6. Notes This section explains notes.  Notes on Using A/D...
  • Page 1959CHAPTER 44: 12-BIT A/D CONVERTER 6. Notes MB91520 Series final activation channel of the continuous scan conversion is executed. ...
  • Page 1960CHAPTER 44: 12-BIT A/D CONVERTER 6. Notes MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 1922 CHAPTER : 12-BIT A/D CONVERTER FUJITSU...
  • Page 1961: CHAPTER 45: FLASH MEMORYCHAPTER 45: FLASH MEMORY 1. Overview MB91520 Series CHAPTER : FLASH MEMORY This chapter explains the flash memory. 1. Overview...
  • Page 1962CHAPTER 45: FLASH MEMORY 1. Overview MB91520 Series 1. Overview This section explains an overview of the flash memory. The...
  • Page 1963CHAPTER 45: FLASH MEMORY 2. Features MB91520 Series 2. Features This section explains features of the flash memory.  Usable...
  • Page 1964CHAPTER 45: FLASH MEMORY 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the flash memory. 3.1...
  • Page 1965CHAPTER 45: FLASH MEMORY 3. Configuration MB91520 Series 3.1. Block Diagram The block diagram of the flash memory is shown...
  • Page 1966CHAPTER 45: FLASH MEMORY 3. Configuration MB91520 Series 3.2. Sector Configuration Diagram The sector configuration diagram of the flash memory...
  • Page 1967CHAPTER 45: FLASH MEMORY 3. Configuration MB91520 Series Figure 3-4 Sector Configuration Diagram (MB91F524) 512+64kB configuration Small sector configuration unit...
  • Page 1968CHAPTER 45: FLASH MEMORY 3. Configuration MB91520 Series Figure 3-6 Sector Configuration Diagram (MB91F526) 1024+64kB configuration Address Small sector configuration...
  • Page 1969CHAPTER 45: FLASH MEMORY 3. Configuration MB91520 Series 3.3. Sector Number and Flash Macro Number Correspondence Chart A sector configuration...
  • Page 1970CHAPTER 45: FLASH MEMORY 3. Configuration MB91520 Series Table 3-2 Sector number table MB91F523 (384+64KB Products) Sector Sector Address Remark...
  • Page 1971CHAPTER 45: FLASH MEMORY 3. Configuration MB91520 Series Table 3-3 Sector number table MB91F524 (512+64KB Products) Sector Sector Address Remark...
  • Page 1972CHAPTER 45: FLASH MEMORY 3. Configuration MB91520 Series Table 3-4 Sector number table MB91F525 (768+64KB Products) Sector Sector Address Remark...
  • Page 1973CHAPTER 45: FLASH MEMORY 3. Configuration MB91520 Series Sector Sector Address Remark number size 0x12_0000 to 0x13_FFFB SA18 64KB (Lower...
  • Page 1974CHAPTER 45: FLASH MEMORY 3. Configuration MB91520 Series Sector Sector Address Remark number size Reserved Interrupt vector table position (Default...
  • Page 1975CHAPTER 45: FLASH MEMORY 4. Registers MB91520 Series 4. Registers This section explains registers of the flash memory. Table 4-1...
  • Page 1976CHAPTER 45: FLASH MEMORY 4. Registers MB91520 Series 4.1. Flash Control Register : FCTLR (Flash ConTroL Register) The bit configuration...
  • Page 1977CHAPTER 45: FLASH MEMORY 4. Registers MB91520 Series FSZ[1:0] Description 00 8-bit 01/10/11 16-bit [bit9, bit8] FAW[1:0] (FLASH Access Wait)...
  • Page 1978CHAPTER 45: FLASH MEMORY 4. Registers MB91520 Series 4.2. Flash Status Register : FSTR (Flash STatus Register) The bit configuration...
  • Page 1979CHAPTER 45: FLASH MEMORY 4. Registers MB91520 Series FRDY Description 0 Operation in progress (write/erase disabled, read status enabled) 1...
  • Page 1980CHAPTER 45: FLASH MEMORY 4. Registers MB91520 Series 4.3. Flash Interface Control Register : FLIFCTLR(Flash I/F Control Register) The bit...
  • Page 1981CHAPTER 45: FLASH MEMORY 4. Registers MB91520 Series 4.4. Flash I/F Feature Extension Register 1: FLIFFER1 The bit configuration of...
  • Page 1982CHAPTER 45: FLASH MEMORY 4. Registers MB91520 Series 4.5. Flash I/F Feature Extension Register 2: FLIFFER2 The bit configuration of...
  • Page 1983CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5. Operation This section explains operations of the flash memory. 5.1. Access...
  • Page 1984CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.1. Access Mode Setting The access mode setting is shown below. The...
  • Page 1985CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.1.1. Configuring CPU-ROM Mode Configuring CPU-ROM mode is shown below. When the...
  • Page 1986CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.1.2. Configuring CPU Programming Mode Configuring CPU programming mode is shown below....
  • Page 1987CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.2. Programming Flash Memory by CPU This section explains programming flash memory...
  • Page 1988CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.3. Automatic Algorithm This section explains the automatic algorithm. When using CPU...
  • Page 1989CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.3.1. Command Sequence The command sequence is shown below. The automatic algorithm...
  • Page 1990CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series Note: If an incorrect address value or data value is written, or...
  • Page 1991CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series  Chip Erase Command If the chip erase command is sent to...
  • Page 1992CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.3.2. Automatic Algorithm Execution State This section explains the automatic algorithm execution...
  • Page 1993CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series  Each bit and flash memory status Table 5-2 shows the correspondence...
  • Page 1994CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series Note: When the automatic algorithm is running, the data for the specified...
  • Page 1995CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series [bit3] SETI : Sector erase timer flag bit During sector erase, a...
  • Page 1996CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.4. Reset Command The reset command is explained. The flash memory can...
  • Page 1997CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.5. Write Command The write command is shown below Writes are performed...
  • Page 1998CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series Figure 5-2 Example of Write Procedure Start of writing Set the FWE...
  • Page 1999CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series Notes: ⋅ Once the write has finished, because the flash memory returns...
  • Page 2000CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.6. Chip Erase Command The chip erase command is shown below. The...
  • Page 2001CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.7. Sector Erase Command The sector erase command is shown below. A...
  • Page 2002CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series Figure 5-3 Example of Sector Erase Procedure Start of erase Set the...
  • Page 2003CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series Notes: ⋅ The time required to erase the sector is [(sector erase...
  • Page 2004CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.8. Sector Erase Suspend Command The sector erase suspend command is shown...
  • Page 2005CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.9. Security Function The security function is shown below. This flash memory...
  • Page 2006CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.9.1. Flash Security On/Off Determination When Reset Released Flash security on/off determination...
  • Page 2007CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.9.2. Flash Security Setting Method The flash security setting method is shown...
  • Page 2008CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.9.3. Unlocking Flash Security Unlocking flash security is shown below. The chip...
  • Page 2009CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.9.4. Flash Access Restrictions When Security is ON Flash access restrictions when...
  • Page 2010CHAPTER 45: FLASH MEMORY 5. Operation MB91520 Series 5.10. Notes on Using Flash Memory Notes on using flash memory are...
  • Page 2011: CHAPTER 46: WORKFLASH MEMORYCHAPTER 46: WORKFLASH MEMORY 1. Overview MB91520 Series CHAPTER : WORKFLASH MEMORY This chapter explains the WorkFlash memory. 1. Overview...
  • Page 2012CHAPTER 46: WORKFLASH MEMORY 1. Overview MB91520 Series 1. Overview This section explains the overview of the WorkFlash memory. The...
  • Page 2013CHAPTER 46: WORKFLASH MEMORY 2. Features MB91520 Series 2. Features This section explains features of the WorkFlash memory. ⋅ Usable...
  • Page 2014CHAPTER 46: WORKFLASH MEMORY 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the WorkFlash memory. 3.1....
  • Page 2015CHAPTER 46: WORKFLASH MEMORY 3. Configuration MB91520 Series 3.1. Block Diagram This section shows the block diagram of the WorkFlash...
  • Page 2016CHAPTER 46: WORKFLASH MEMORY 3. Configuration MB91520 Series 3.2. Sector Configuration Diagram The sector configuration diagram of the WorkFlash memory...
  • Page 2017CHAPTER 46: WORKFLASH MEMORY 4. Registers MB91520 Series 4. Registers This section explains registers of the WorkFlash memory. Table 4-1...
  • Page 2018CHAPTER 46: WORKFLASH MEMORY 4. Registers MB91520 Series 4.1. WorkFlash Control Register : DFCTLR (WorkFlash ConTroL Register) The bit configuration...
  • Page 2019CHAPTER 46: WORKFLASH MEMORY 4. Registers MB91520 Series 4.2. WorkFlash Status Register : DFSTR (WorkFlash STatus Register) The bit configuration...
  • Page 2020CHAPTER 46: WORKFLASH MEMORY 4. Registers MB91520 Series [bit0]DFRDY (WorkFlash ReaDY) : WorkFlash write enable This bit indicates whether the...
  • Page 2021CHAPTER 46: WORKFLASH MEMORY 4. Registers MB91520 Series 4.3. Flash Interface Control Register : FLIFCTLR (Flash I/F Control Register) The...
  • Page 2022CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5. Operation The section explains the operation of the WorkFlash memory. This...
  • Page 2023CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.1. Access Mode Setting Access mode setting is shown below. The flash...
  • Page 2024CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.1.1. Configuring CPU-ROM Mode below Configuring CPU-ROM mode is shown below. When...
  • Page 2025CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.1.2. Configuring CPU Programming Mode Configuring CPU programming mode is shown below....
  • Page 2026CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.2. Writing Flash Memory by CPU Writing the flash memory by CPU...
  • Page 2027CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.3. Automatic Algorithm The automatic algorithm is shown below. When using CPU...
  • Page 2028CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.3.1. Command Sequence The command sequence is shown below. The automatic algorithm...
  • Page 2029CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series Note: Do as follows to LSB 2-bit of the sector address (SA)...
  • Page 2030CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series Notes: ⋅ When writing in half-word, if the forth command (write data...
  • Page 2031CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series  Sector Erase Command If the sector erase command is sent to...
  • Page 2032CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.3.2. Automatic Algorithm Execution State The automatic algorithm execution state is shown...
  • Page 2033CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series  Each bit and flash memory status Following table shows the correspondence...
  • Page 2034CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series Note: When the automatic algorithm is running, the data for the specified...
  • Page 2035CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series [bit4] Undefined bit [bit3] SETI (Sector erase timer flag bit) During sector...
  • Page 2036CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.4. Reset Command The reset command is shown below. The flash memory...
  • Page 2037CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.5. Write Command The write command is shown below. Writes are performed...
  • Page 2038CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series Figure 5-2 Example of Write Procedure Start of writing Set Setthe the...
  • Page 2039CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series -It appears to have been written as "1". However, even if it...
  • Page 2040CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.6. Chip Erase Command The chip erase command is shown below. The...
  • Page 2041CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.7. Sector Erase Command The sector erase command is shown below. A...
  • Page 2042CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series Figure 5-3 Example of Sector Erase Procedure Start of erase Set Setthe...
  • Page 2043CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.8. Sector Erase Suspend Command The sector erase suspend command is explained...
  • Page 2044CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.9. Security Function The security function is shown below. This flash memory...
  • Page 2045CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.9.1. Flash Security On/Off Determination When Reset Released Flash security on/off determination...
  • Page 2046CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.9.2. Flash Security Setting Method The flash security setting method is shown...
  • Page 2047CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.9.3. Unlocking Flash Security Unlocking flash security is shown below. The chip...
  • Page 2048CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.9.4. Flash Access Restrictions When Security is ON Flash access restrictions when...
  • Page 2049CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series 5.10. Notes on Using Flash Memory Notes on using the flash memory...
  • Page 2050CHAPTER 46: WORKFLASH MEMORY 5. Operation MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 2012 CHAPTER : WORKFLASH MEMORY FUJITSU SEMICONDUCTOR CONFIDENTIAL...
  • Page 2051: CHAPTER 47: ON CHIP DEBUGGER : OCDCHAPTER 47: ON CHIP DEBUGER (OCD) 1. Overview MB91520 Series CHAPTER : ON CHIP DEBUGGER : OCD This chapter explains...
  • Page 2052CHAPTER 47: ON CHIP DEBUGER (OCD) 1. Overview MB91520 Series 1. Overview This section explains the overview of the on...
  • Page 2053CHAPTER 47: ON CHIP DEBUGER (OCD) 2. Features MB91520 Series 2. Features This section explains features of the on chip...
  • Page 2054CHAPTER 47: ON CHIP DEBUGER (OCD) 3. Configuration MB91520 Series 3. Configuration This section shows the configuration of the on...
  • Page 2055CHAPTER 47: ON CHIP DEBUGER (OCD) 3. Configuration MB91520 Series Figure 3-2 OCD Connection Diagram User system Tool software DEBUG...
  • Page 2056CHAPTER 47: ON CHIP DEBUGER (OCD) 3. Configuration MB91520 Series 3.1. DEBUG I/F Clock DEBUG I/F clock is shown. See...
  • Page 2057CHAPTER 47: ON CHIP DEBUGER (OCD) 3. Configuration MB91520 Series 3.1.1. DEBUG I/F Main Clock : M_MCLK DEBUG I/F main...
  • Page 2058CHAPTER 47: ON CHIP DEBUGER (OCD) 3. Configuration MB91520 Series 3.1.2. DEBUG I/F PLL Clock : M_PCLK DEBUG I/F PLL...
  • Page 2059CHAPTER 47: ON CHIP DEBUGER (OCD) 4. Registers MB91520 Series 4. Registers This section explains the registers of the on-chip...
  • Page 2060CHAPTER 47: ON CHIP DEBUGER (OCD) 4. Registers MB91520 Series 4.1. DBG Register The bit configuration of the DBG register...
  • Page 2061CHAPTER 47: ON CHIP DEBUGER (OCD) 4. Registers MB91520 Series 4.1.1. DSU Control Register : DSUCR The DSU control register...
  • Page 2062CHAPTER 47: ON CHIP DEBUGER (OCD) 4. Registers MB91520 Series 4.2. User IO Register The bit configuration of the User...
  • Page 2063CHAPTER 47: ON CHIP DEBUGER (OCD) 4. Registers MB91520 Series 4.2.1. User Event Register : UER The user event register...
  • Page 2064CHAPTER 47: ON CHIP DEBUGER (OCD) 4. Registers MB91520 Series 4.2.2. High-Speed Communication Frequency Register : HSCFR The high-speed communication...
  • Page 2065CHAPTER 47: ON CHIP DEBUGER (OCD) 4. Registers MB91520 Series 4.2.3. Message Buffer : MBR The is message buffer is...
  • Page 2066CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 5. Operation This section explains the operation of the on-chip...
  • Page 2067CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 5.1. OCDU Operating Mode OCDU operating mode is shown. 5.1.1...
  • Page 2068CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 5.1.1. Operating Mode Operating mode is shown. The OCDU operating...
  • Page 2069CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 5.1.2. Operating Mode Status Transition Operating mode status transition is...
  • Page 2070CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 5.2. Overview of DEBUG I/F The overview of DEBUG I/F...
  • Page 2071CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 5.2.1. Chip Reset Sequence Chip reset sequence is shown. When...
  • Page 2072CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series The relationship between the number of sampling clock cycles of...
  • Page 2073CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 5.2.2. Security Function Security function is shown. OCDU has the...
  • Page 2074CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 5.3. Specification Restrictions at Connection to OCD Tool of This...
  • Page 2075CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 5.3.1. Clock Setting Clock setting is shown. ⋅ When the...
  • Page 2076CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 5.3.2. Standby Mode Standby mode is shown. ⋅ Even if...
  • Page 2077CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 5.3.3. Clock Reset State Transitions Clock reset state transitions is...
  • Page 2078CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series *1 : There is a register not reset when returning...
  • Page 2079CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 5.3.4. Summary of Specification Restrictions Summary of specification restrictions is...
  • Page 2080CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series Difference from when the OCD tool is not connected Reset...
  • Page 2081CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series Processing time difference Interrupt factor from when the OCD tool...
  • Page 2082CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 2) Communication mode (*1): High-speed UART/phase modulation UART Difference from...
  • Page 2083CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series Processing time difference Interrupt factor from when the OCD tool...
  • Page 2084CHAPTER 47: ON CHIP DEBUGER (OCD) 5. Operation MB91520 Series 5.4. OCD-DSU ID Code and Mount Type Information on This...
  • Page 2085: CHAPTER 48: WAVEFORM GENERATORCHAPTER 48: WAVEFORM GENERATOR 1. Overview MB91520 Series CHAPTER : WAVEFORM GENERATOR This chapter explains the waveform generator. 1. Overview...
  • Page 2086CHAPTER 48: WAVEFORM GENERATOR 1. Overview MB91520 Series 1. Overview This section explains the overview of the waveform generator. When...
  • Page 2087CHAPTER 48: WAVEFORM GENERATOR 2. Features MB91520 Series 2. Features This section explains the features of the waveform generator. ...
  • Page 2088CHAPTER 48: WAVEFORM GENERATOR 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the waveform generator. ...
  • Page 2089CHAPTER 48: WAVEFORM GENERATOR 3. Configuration MB91520 Series  Pin Application of the Waveform Generator Table 3-1 shows the pin...
  • Page 2090CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series 4. Registers This section explains the register of the waveform generator. ...
  • Page 2091CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series 4.1. Registers for the Waveform Generator This section explains the register of...
  • Page 2092CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series 4.1.1. 16-bit Dead Timer Register (TMRR) The bit configuration for the 16-bit...
  • Page 2093CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series 4.1.2. 16-bit Dead Timer State Control Register (DTSCR) The bit configuration for...
  • Page 2094CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series [bit4] TMIF0: Interrupt request flag bit Function TMIF0 Read Write 0 No...
  • Page 2095CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series [bit2 to bit0] TMD2 to TMD0: Operation mode bits TMD2 TMD1 TMD0...
  • Page 2096CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series  DTSCR1: Address 12A9H (Access: Byte, Half-word, Word) bit7 bit6 bit5 bit4...
  • Page 2097CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series [bit4] TMIF1: Interrupt request flag bit Function TMIF1 Read Write 0 No...
  • Page 2098CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series [bit2 to bit0] TMD5 to TMD3 : Operation mode bits TMD5 TMD4...
  • Page 2099CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series  DTSCR2: Address 12AAH (Access: Byte, Half-word, Word) bit7 bit6 bit5 bit4...
  • Page 2100CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series [bit4] TMIF2: Interrupt request flag bit Function TMIF2 Read Write 0 No...
  • Page 2101CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series [bit2 to bit0] TMD8 to TMD6: Operation mode bits TMD8 TMD7 TMD6...
  • Page 2102CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series 4.1.3. 16-bit Dead Timer Reload Interrupt Register (DTIR) The bit configuration for...
  • Page 2103CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series ⋅ This bit will be cleared when the dead timer interrupt clear...
  • Page 2104CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series 4.1.4. 16-bit Dead Timer Minus Control Register (DTMNS) The bit configuration for...
  • Page 2105CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series [bit2] MNS2: Dead time function selection bit (RTO4 and RTO5) MNS2 Function...
  • Page 2106CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series 4.1.5. Waveform Control Register 1/2 (SIGCR1, SIGCR2) The bit configuration for the...
  • Page 2107CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series Notes: To cancel the noise pulse width, you will need an approximately...
  • Page 2108CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series  SIGCR20: Address 12B3H (Access: Byte, Half-word, Word) bit7 bit6 bit5 bit4...
  • Page 2109CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series 4.1.6. PPG Output Control Register (PICS) The bit configuration for the PPG...
  • Page 2110CHAPTER 48: WAVEFORM GENERATOR 4. Registers MB91520 Series [bit28] PGEN2: PPG output enable bit PGEN2 Function 0 Disable PPG output...
  • Page 2111CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series 5. Operation This section explains the operation. 5.1. Interrupts for Waveform Generator...
  • Page 2112CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series 5.1. Interrupts for Waveform Generator The interrupts for waveform generator is explained....
  • Page 2113CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series 5.2. Operation of the Waveform Generator The operation of the waveform generator...
  • Page 2114CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series  Pins and Bit Setting Pin application table for RTO/GATE output state...
  • Page 2115CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series PPG output control PPG output to the RTO0 to RTO5 pins can...
  • Page 2116CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series  GATE signal generation when the GATE is active and each OUT...
  • Page 2117CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series Note: Each 16-bit dead timer will be used for two OUTs. In...
  • Page 2118CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series Operation in timer mode If a rising edge of the OUT0 to...
  • Page 2119CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series Operation of the dead time timer mode The dead time generator inputs...
  • Page 2120CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series  Non-overlap signal generation of minus control by the inverted polarity OUT1,...
  • Page 2121CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series  Non-overlap signal generation of minus control by the normal polarity OUT1,...
  • Page 2122CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series  Non-overlap signal generation by the inverted polarity OUT1, OUT3, and OUT5...
  • Page 2123CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series Operation of the dead time timer mode (precautions)  Signal generation Default...
  • Page 2124CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series  When the "H" interval of the compare output is long (or...
  • Page 2125CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series Figure 5-11 When the "H" Interval of the Compare Output Is Short...
  • Page 2126CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series Figure 5-12 When the compare output transition time is short and reload...
  • Page 2127CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series  Changing from normal mode to inverted mode while the dead time...
  • Page 2128CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series  Changing the minus control mode while the dead time timer mode...
  • Page 2129CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series Operation of the DTTI pin control You will be able to control...
  • Page 2130CHAPTER 48: WAVEFORM GENERATOR 5. Operation MB91520 Series  DTTI Pin Noise Cancellation Feature When you set the NRSL of...
  • Page 2131CHAPTER 48: WAVEFORM GENERATOR 6. Notes MB91520 Series 6. Notes This section explains the notes. Notes on Using the Waveform...
  • Page 2132CHAPTER 48: WAVEFORM GENERATOR 6. Notes MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 2094 CHAPTER : WAVEFORM GENERATOR FUJITSU SEMICONDUCTOR CONFIDENTIAL...
  • Page 2133: CHAPTER 49: BUS DIAGNOSIS FUNCTIONCHAPTER 49: BUS DIAGNOSIS FUNCTION 1. Overview MB91520 Series CHAPTER : BUS DIAGNOSIS FUNCTION This chapter explains the bus diagnosis...
  • Page 2134CHAPTER 49: BUS DIAGNOSIS FUNCTION 1. Overview MB91520 Series 1. Overview This section explains the overview of BUS diagnosis function....
  • Page 2135CHAPTER 49: BUS DIAGNOSIS FUNCTION 2. Features MB91520 Series 2. Features This section explains the features of BUS diagnosis function....
  • Page 2136CHAPTER 49: BUS DIAGNOSIS FUNCTION 3. Configuration MB91520 Series 3. Configuration This section explains the Configuration of BUS diagnosis function....
  • Page 2137CHAPTER 49: BUS DIAGNOSIS FUNCTION 3. Configuration MB91520 Series Figure 3-2 Bus diagnosis target area diagram The part enclosed with...
  • Page 2138CHAPTER 49: BUS DIAGNOSIS FUNCTION 3. Configuration MB91520 Series Notes: The following address areas are excluded from bus diagnosis target....
  • Page 2139CHAPTER 49: BUS DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4. Registers This section explains the registers of bus diagnosis function....
  • Page 2140CHAPTER 49: BUS DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.1. Bus Diagnosis Status Register : BUSDIGSR This section explains the...
  • Page 2141CHAPTER 49: BUS DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit11 to bit8] AER3 to AER0: Address parity error Address parity...
  • Page 2142CHAPTER 49: BUS DIAGNOSIS FUNCTION 4. Registers MB91520 Series Notes: ⋅ Bus diagnosis status register 0 (BUSDIGSR0) indicates AHB bus...
  • Page 2143CHAPTER 49: BUS DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.2. Bus Diagnosis Test Register : BUSTSTR0/1 This section explains the...
  • Page 2144CHAPTER 49: BUS DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit10] RBEN: Rbus parity error generation enable This bit enables the...
  • Page 2145CHAPTER 49: BUS DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit3 to bit0] AEN3 to AEN0: Address error Address error setting...
  • Page 2146CHAPTER 49: BUS DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit13, bit12] Undefined "0" is always read. Writing does not affect...
  • Page 2147CHAPTER 49: BUS DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit7 to bit4] DEN3 to DEN0: Data error Data error setting...
  • Page 2148CHAPTER 49: BUS DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.3. Bus Diagnosis Address Register : BUSADR This section explains the...
  • Page 2149CHAPTER 49: BUS DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit31 to bit0] ADR31 to ADR0: Bus address If an address...
  • Page 2150CHAPTER 49: BUS DIAGNOSIS FUNCTION 5. Operation MB91520 Series 5. Operation This section explains the Operation of bus diagnosis function....
  • Page 2151CHAPTER 49: BUS DIAGNOSIS FUNCTION 5. Operation MB91520 Series 5.1. Error detection This section explains the Error detection of bus...
  • Page 2152CHAPTER 49: BUS DIAGNOSIS FUNCTION 5. Operation MB91520 Series  NMI request generation/stop NMI request is continued while either error...
  • Page 2153CHAPTER 49: BUS DIAGNOSIS FUNCTION 5. Operation MB91520 Series 5.2. Test function This section explains the test function of bus...
  • Page 2154CHAPTER 49: BUS DIAGNOSIS FUNCTION 5. Operation MB91520 Series 5.3. Notes This section explains the notes of bus diagnosis function....
  • Page 2155CHAPTER 49: BUS DIAGNOSIS FUNCTION 5. Operation MB91520 Series 5.4. Example of operating bus diagnosis This section explains the Example...
  • Page 2156CHAPTER 49: BUS DIAGNOSIS FUNCTION 5. Operation MB91520 Series  Bus Diagnosis Operation Flow The operation flow of the bus...
  • Page 2157CHAPTER 49: BUS DIAGNOSIS FUNCTION 5. Operation MB91520 Series (2) At register writing Start Address output from the CPU CPU...
  • Page 2158CHAPTER 49: BUS DIAGNOSIS FUNCTION 5. Operation MB91520 Series (3) Processing at error detection The following gives an example of...
  • Page 2159CHAPTER 49: BUS DIAGNOSIS FUNCTION 5. Operation MB91520 Series ⋅ During Operation NMI generation n=0 BUSDIGSRn read YES Parity error?...
  • Page 2160CHAPTER 49: BUS DIAGNOSIS FUNCTION 5. Operation MB91520 Series ⋅ In the Test Mode Start (BUSTSTR:KEY1,BUSTSTR:KEY0)=(00), bit13-bit0=Y write (BUSTSTR:KEY1,BUSTSTR:KEY0)=(01), bit13-bit0=Y...
  • Page 2161: CHAPTER 50: RAM DIAGNOSIS FUNCTIONCHAPTER 50: RAM DIAGNOSIS FUNCTION 1. Overview MB91520 Series CHAPTER : RAM DIAGNOSIS FUNCTION This chapter explains the RAM diagnosis...
  • Page 2162CHAPTER 50: RAM DIAGNOSIS FUNCTION 1. Overview MB91520 Series 1. Overview This section is explains overview of RAM diagnosis function....
  • Page 2163CHAPTER 50: RAM DIAGNOSIS FUNCTION 2. Features MB91520 Series 2. Features This section explains feature of RAM diagnosis function. ...
  • Page 2164CHAPTER 50: RAM DIAGNOSIS FUNCTION 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of RAM diagnosis function....
  • Page 2165CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4. Registers This section explains the registers of RAM diagnosis function....
  • Page 2166CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.1. TEST Error Address Register 0 XBS RAM : TEAR0X This...
  • Page 2167CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit14 to bit0] D14 to D0: Error generation address bits During...
  • Page 2168CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.2. TEST Error Address Register 1 XBS RAM : TEAR1X This...
  • Page 2169CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit14 to bit0] D14 to D0: Error generation address bits During...
  • Page 2170CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.3. TEST Error Address Register 2 XBS RAM : TEAR2X This...
  • Page 2171CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit14 to bit0] D14 to D0: Error generation address bits During...
  • Page 2172CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.4. TEST Start Address Register XBS RAM : TASARX This section...
  • Page 2173CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.5. TEST End Address Register XBS RAM : TAEARX This section...
  • Page 2174CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.6. TEST Diagnosis Function Register XBS RAM : TTCRX This section...
  • Page 2175CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit7] TEIE: Interrupt enable bit resulting from a diagnosis error TEIE...
  • Page 2176CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit4] TCI: Diagnosis end bit TCI Function Read: The RAM diagnosis...
  • Page 2177CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.7. TEST Initialization Function Register XBS RAM : TICRX This section...
  • Page 2178CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit1] ITYP: RAM initialization content indication bit ITYP Function 0 Initialization...
  • Page 2179CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.8. TEST Soft Reset Generation Control Register XBS RAM : TSRCRX...
  • Page 2180CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.9. TEST Fake Error Generation Control Register XBS RAM : TFECRX...
  • Page 2181CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.10. TEST Key Code Control Register XBS RAM : TKCCRX This...
  • Page 2182CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.11. TEST Error Address Register 0 BACKUP-RAM : TEAR0A This section...
  • Page 2183CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit28 to bit11] Reserved Reserved bits. These bits read out "0"....
  • Page 2184CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.12. TEST Error Address Register 1 BACKUP-RAM : TEAR1A This section...
  • Page 2185CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit28 to bit11] Reserved Reserved bits. These bits read out "0"....
  • Page 2186CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.13. TEST Error Address Register 2 BACKUP-RAM : TEAR2A This section...
  • Page 2187CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit28 to bit11] Reserved Reserved bits. These bits read out "0"....
  • Page 2188CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.14. TEST Start Address Register BACKUP-RAM : TASARA This section explains...
  • Page 2189CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.15. TEST End Address Register BACKUP-RAM : TAEARA This section explains...
  • Page 2190CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.16. TEST Diagnosis Function Register BACKUP-RAM : TTCRA This section explains...
  • Page 2191CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit7] TEIE: Interrupt enable bit resulting from a diagnosis error TEIE...
  • Page 2192CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit4] TCI: Diagnosis end bit TCI Function Read: The RAM diagnosis...
  • Page 2193CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.17. TEST Initialization Function Register BACKUP-RAM : TICRA This section explains...
  • Page 2194CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series [bit1] ITYP: RAM initialization content indication bit ITYP Function 0 Initialization...
  • Page 2195CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.18. TEST Soft Reset Generation Control Register BACKUP-RAM : TSRCRA This...
  • Page 2196CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.19. TEST Fake Error Generation Control Register BACKUP-RAM : TFECRA This...
  • Page 2197CHAPTER 50: RAM DIAGNOSIS FUNCTION 4. Registers MB91520 Series 4.20. TEST Key Code Control Register BACKUP-RAM : TKCCRA This section...
  • Page 2198CHAPTER 50: RAM DIAGNOSIS FUNCTION 5. Operation MB91520 Series 5. Operation This section explains the Operation of RAM diagnosis. 5.1....
  • Page 2199CHAPTER 50: RAM DIAGNOSIS FUNCTION 5. Operation MB91520 Series 5.1. RAM Diagnosis This section explains the RAM diagnosis. XBS RAM...
  • Page 2200CHAPTER 50: RAM DIAGNOSIS FUNCTION 5. Operation MB91520 Series 5.2. RAM Initialization This section explains the RAM initialization. Only either...
  • Page 2201CHAPTER 50: RAM DIAGNOSIS FUNCTION 5. Operation MB91520 Series 5.3. Interrupt-Related Register This section explains the interrupt-related register. To generate...
  • Page 2202CHAPTER 50: RAM DIAGNOSIS FUNCTION 5. Operation MB91520 Series 5.4. RAM Diagnosis Fake Error Generation Procedure This section explains the...
  • Page 2203CHAPTER 50: RAM DIAGNOSIS FUNCTION 5. Operation MB91520 Series 5.5. Number of Required Cycles This section explains the number of...
  • Page 2204CHAPTER 50: RAM DIAGNOSIS FUNCTION 5. Operation MB91520 Series (3) "RAM diagnosis (march)" ⋅ Write (1 × 3 cycles) ⋅...
  • Page 2205CHAPTER 50: RAM DIAGNOSIS FUNCTION 5. Operation MB91520 Series 5.6. Note This section explains the note. Accessing to RAM is...
  • Page 2206CHAPTER 50: RAM DIAGNOSIS FUNCTION 5. Operation MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 2168 CHAPTER : RAM DIAGNOSIS FUNCTION FUJITSU...
  • Page 2207: CHAPTER 51: TIMING PROTECTION UNITCHAPTER 51: TIMING PROTECTION UNIT 1. Overview MB91520 Series CHAPTER : TIMING PROTECTION UNIT This chapter explains the Timing Protection...
  • Page 2208CHAPTER 51: TIMING PROTECTION UNIT 1. Overview MB91520 Series 1. Overview This section explains the overview of the Timing Protection...
  • Page 2209CHAPTER 51: TIMING PROTECTION UNIT 2. Features MB91520 Series 2. Features This section explains features of the Timing Protection Unit....
  • Page 2210CHAPTER 51: TIMING PROTECTION UNIT 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of the Timing Protection...
  • Page 2211CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series 4. Registers This section explains registers of the Timing Protection Unit....
  • Page 2212CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series 4.1. TPU Unlock Register : TPUUNLOCK The bit configuration of TPU...
  • Page 2213CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series 4.2. TPU Lock Status Register : TPULST The bit configuration of...
  • Page 2214CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series 4.3. TPU Access Violation Status Register : TPUVST The bit configuration...
  • Page 2215CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series 4.4. TPU Configuration Register : TPUCFG The bit configuration of TPU...
  • Page 2216CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series [bit23] GLBPSE (Global Prescaler Enable) : Global prescaler operation permission The...
  • Page 2217CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series 4.5. TPU Timer Interrupt Request Register : TPUTIR The bit configuration...
  • Page 2218CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series 4.6. TPU Timer Status Register : TPUTST The bit configuration of...
  • Page 2219CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series 4.7. TPU Timer Interrupt Enable Register : TPUTIE The bit configuration...
  • Page 2220CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series 4.8. TPU Module ID Register : TPUTMID The bit configuration of...
  • Page 2221CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series 4.9. TPU Timer Control Register 00 to 07 : TPUTCN00 to...
  • Page 2222CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series [bit29] CONT (Continue) : Timer operation restart This bit is used...
  • Page 2223CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series 4.10. TPU Timer Control Register 10 to 17 : TPUTCN10 to...
  • Page 2224CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series [bit1, bit0] PS[1:0] (Individual Prescaler) : Timer prescaler setting The prescaler...
  • Page 2225CHAPTER 51: TIMING PROTECTION UNIT 4. Registers MB91520 Series 4.11. TPU Timer Current Count Register 0 to 7 : TPUTCC0...
  • Page 2226CHAPTER 51: TIMING PROTECTION UNIT 5. Operation MB91520 Series 5. Operation The section explains the operation. MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED...
  • Page 2227CHAPTER 51: TIMING PROTECTION UNIT 5. Operation MB91520 Series 5.1. TPU Control Register Access Protection The section explains the TPU...
  • Page 2228CHAPTER 51: TIMING PROTECTION UNIT 5. Operation MB91520 Series 5.2. Global Prescaler The section explains the global prescaler. The global...
  • Page 2229CHAPTER 51: TIMING PROTECTION UNIT 5. Operation MB91520 Series 5.3. Interrupt Control The section explains the Interrupt Control. The generation...
  • Page 2230CHAPTER 51: TIMING PROTECTION UNIT 5. Operation MB91520 Series 5.4. Timer Operation The section explains the timer operation. Each timer...
  • Page 2231CHAPTER 51: TIMING PROTECTION UNIT 5. Operation MB91520 Series 5.5. Free-run Function The section explains the free-run function. Each timer...
  • Page 2232CHAPTER 51: TIMING PROTECTION UNIT 5. Operation MB91520 Series 5.6. Individual Prescaler Function The section explains the individual prescaler function....
  • Page 2233CHAPTER 51: TIMING PROTECTION UNIT 5. Operation MB91520 Series 5.7. Debug Support Function The section explains the debug support function....
  • Page 2234CHAPTER 51: TIMING PROTECTION UNIT 5. Operation MB91520 Series 5.8. Operation Flow The section explains the operation flow.  Initialization...
  • Page 2235: CHAPTER 52: CLOCK MONITORCHAPTER 52: CLOCK MONITOR 1. Overview MB91520 Series CHAPTER : CLOCK MONITOR This chapter explains the clock monitor. 1. Overview...
  • Page 2236CHAPTER 52: CLOCK MONITOR 1. Overview MB91520 Series 1. Overview This section explains the overview of clock monitor. The clock...
  • Page 2237CHAPTER 52: CLOCK MONITOR 2. Features MB91520 Series 2. Features This section explains the features of clock monitor. ⋅ Format:...
  • Page 2238CHAPTER 52: CLOCK MONITOR 3. Configuration MB91520 Series 3. Configuration This section explains the configuration of clock monitor. Figure 3-1...
  • Page 2239CHAPTER 52: CLOCK MONITOR 4. Registers MB91520 Series 4. Registers This section explains the registers of clock monitor Table 4-1...
  • Page 2240CHAPTER 52: CLOCK MONITOR 4. Registers MB91520 Series [bit3 to bit0] CMSEL3 to CMSEL0 (Output Source Clock Selection Bits) Selected...
  • Page 2241CHAPTER 52: CLOCK MONITOR 5. Operation Description MB91520 Series 5. Operation Description This section explains operation description of clock monitor...
  • Page 2242CHAPTER 52: CLOCK MONITOR 6. Setup MB91520 Series 6. Setup This section explains the setup of clock monitor. Configuration Setting...
  • Page 2243CHAPTER 52: CLOCK MONITOR 7. Q&A MB91520 Series 7. Q&A This section explains the Q&A of clock monitor 7.1 How...
  • Page 2244CHAPTER 52: CLOCK MONITOR 7. Q&A MB91520 Series 7.1. How Do I Configure the Output Pin (MONCLK)? Setting of the...
  • Page 2245CHAPTER 52: CLOCK MONITOR 7. Q&A MB91520 Series 7.2. How Do I Select the Output Frequency? Selection of the output...
  • Page 2246CHAPTER 52: CLOCK MONITOR 7. Q&A MB91520 Series 7.3. How Do I Enable or Disable Clock Monitor Output? The enable...
  • Page 2247CHAPTER 52: CLOCK MONITOR 7. Q&A MB91520 Series 7.4. How Do I Set the Clock Output Mark Level? Setting of...
  • Page 2248CHAPTER 52: CLOCK MONITOR 8. Notes MB91520 Series 8. Notes This section explains the note of clock monitor. In order...
  • Page 2249: APPENDIXAPPENDIX A. I/O Map MB91520 Series APPENDIX Appendix is shown. A. I/O Map B. List of Interrupt Vector C. Pins...
  • Page 2250APPENDIX A. I/O Map MB91520 Series A. I/O Map IO map is shown. The following I/O map shows the relationship...
  • Page 2251APPENDIX A. I/O Map MB91520 Series Table A-1 : I/O Map Address offset value / Register name Address Block +0...
  • Page 2252APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 OCLS89 [R/W]...
  • Page 2253APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 OCCP8 [R/W]...
  • Page 2254APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 CPCLR3 [R/W]...
  • Page 2255APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 PABR2 [R/W]...
  • Page 2256APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 IRPR0H [R]...
  • Page 2257APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 000470H to...
  • Page 2258APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 MTMCR [R/W]...
  • Page 2259APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 REGSEL [R/W]...
  • Page 2260APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 AWR2 [R/W]...
  • Page 2261APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 WRAR03 [R/W]...
  • Page 2262APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 WRDR14 [R/W]...
  • Page 2263APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 TPUTCN13 [R/W]...
  • Page 2264APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 DSAR0 [R/W]...
  • Page 2265APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 DSAR6 [R/W]...
  • Page 2266APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 DCCR12 [R/W]...
  • Page 2267APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 DDR08 [R/W]...
  • Page 2268APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 EPFR08 [R/W]...
  • Page 2269APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 000EDCH to...
  • Page 2270APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 CPCLR5 [R/W]...
  • Page 2271APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 001140H to...
  • Page 2272APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 001264H to...
  • Page 2273APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 ADCOMP0/ADCOMPB0[R/W] H,W...
  • Page 2274APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 ADTCS12[R/W] B,H,W...
  • Page 2275APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 ADTCD26[R] B,H,W...
  • Page 2276APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 ADRCCS0[R/W] ADRCCS1[R/W]...
  • Page 2277APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 ADSTPCS4[R/W] ADSTPCS5[R/W]...
  • Page 2278APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 0014D8H to...
  • Page 2279APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 ADRCUT7[R/W] B,H,W...
  • Page 2280APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 0015D4H to...
  • Page 2281APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 SCR1/(IBCR1) [R/W]...
  • Page 2282APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 SCR2/(IBCR2)[R/W] ESCR2/(IBSR2)[R/W]...
  • Page 2283APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 SCR3/(IBCR3) [R/W]...
  • Page 2284APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 SCR4/(IBCR4) [R/W]...
  • Page 2285APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 SCR5/(IBCR5) [R/W]...
  • Page 2286APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 SCR6/(IBCR6) [R/W]...
  • Page 2287APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 SCR7/(IBCR7) [R/W]...
  • Page 2288APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 SCR8/(IBCR8) [R/W]...
  • Page 2289APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 SCR9/(IBCR9) [R/W]...
  • Page 2290APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 SCR10/(IBCR10) ESCR10/(IBSR10)...
  • Page 2291APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 SCR11/(IBCR11) ESCR11/(IBSR11)...
  • Page 2292APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 GTRS8 [R/W]...
  • Page 2293APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 PCN201 [R/W]...
  • Page 2294APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 PTPC4 [R/W]...
  • Page 2295APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 PCN210 [R/W]...
  • Page 2296APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 PDUT16 [W]...
  • Page 2297APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 PCN22 [R/W]...
  • Page 2298APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 PCN28 [R/W]...
  • Page 2299APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 PTPC33 [R/W]...
  • Page 2300APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 PCN239 [R/W]...
  • Page 2301APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 PDUT45 [W]...
  • Page 2302APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 002028H ―...
  • Page 2303APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 INTPND40 [R]...
  • Page 2304APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 IF2CREQ1 [R/W]...
  • Page 2305APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 0021B8H ―...
  • Page 2306APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 IF2DTB12 [R/W]...
  • Page 2307APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 FLIFCTLR [R/W]...
  • Page 2308APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 TFECRA [R/W]...
  • Page 2309APPENDIX A. I/O Map MB91520 Series Address offset value / Register name Address Block +0 +1 +2 +3 PSSR [R/W]...
  • Page 2310APPENDIX B. List of Interrupt Vector MB91520 Series B. List of Interrupt Vector List of Interrupt Vector is shown. This...
  • Page 2311APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2312APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2313APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2314APPENDIX B. List of Interrupt Vector MB91520 Series Table B-2 Interrupt Vector MB91F52xD (80pin) Interrupt Default number Interrupt RN Interrupt...
  • Page 2315APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2316APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2317APPENDIX B. List of Interrupt Vector MB91520 Series (*1) The status of the multi-function serial interface does not support the...
  • Page 2318APPENDIX B. List of Interrupt Vector MB91520 Series Table B-3 Interrupt Vector MB91F52xF (100pin) Interrupt Default number Interrupt RN Interrupt...
  • Page 2319APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2320APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2321APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2322APPENDIX B. List of Interrupt Vector MB91520 Series Table B-4 Interrupt Vector MB91F52xJ (120pin) Interrupt Default number Interrupt RN Interrupt...
  • Page 2323APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2324APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2325APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2326APPENDIX B. List of Interrupt Vector MB91520 Series Table B-5 Interrupt Vector MB91F52xK (144pin) Interrupt Default number Interrupt RN Interrupt...
  • Page 2327APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2328APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2329APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2330APPENDIX B. List of Interrupt Vector MB91520 Series Table B-6 Interrupt Vector MB91F52xL (176pin) Interrupt Default number Interrupt RN Interrupt...
  • Page 2331APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2332APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2333APPENDIX B. List of Interrupt Vector MB91520 Series Interrupt Default number Interrupt RN Interrupt factor level Offset address for Decimal...
  • Page 2334APPENDIX C. Pins Statuses in State of CPU MB91520 Series C. Pins Statuses in State of CPU Pin statuses in...
  • Page 2335APPENDIX C. Pins Statuses in State of CPU MB91520 Series Pin status after reset factor generation and after reset releasing...
  • Page 2336APPENDIX C. Pins Statuses in State of CPU MB91520 Series Pin status after reset factor generation and after reset releasing...
  • Page 2337APPENDIX C. Pins Statuses in State of CPU MB91520 Series Pin status after reset factor generation and after reset releasing...
  • Page 2338APPENDIX C. Pins Statuses in State of CPU MB91520 Series Pin status after reset factor generation and after reset releasing...
  • Page 2339APPENDIX C. Pins Statuses in State of CPU MB91520 Series Pin status after reset factor generation and after reset releasing...
  • Page 2340APPENDIX C. Pins Statuses in State of CPU MB91520 Series MN705-00010-1v0-E FUJITSU SEMICONDUCTOR LIMITED 2302 APPENDIX FUJITSU SEMICONDUCTOR CONFIDENTIAL 92...
  • Page 2341 MN705-00010-1v0-E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL FM81S Family 32-BIT MICROCONTROLLER MB91520 Series HARDWARE MANUAL February 2012 the first edition...
  • Page 2342 FUJITSU SEMICONDUCTOR LIMITED エラー! 指定したスタイルは使われていません。 FUJITSU SEMICONDUCTOR CONFIDENTIAL 1
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