Fujitsu FR81S User Manual
CHAPTER 25: 16-BIT OUTPUT COMPARE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 16-BIT OUTPUT COMPARE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
•
OCCP1,3,5: Address 124E
H
, 1256
H
, 125E
H
(Access: Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
OP15
OP14
OP13
OP12
OP11
OP10
OP09
OP08
Initial value
0
0
0
0
0
0
0
0
Attribute
R
R
R
R
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
OP07
OP06
OP05
OP04
OP03
OP02
OP01
OP00
Initial value
0
0
0
0
0
0
0
0
Attribute
R
R
R
R
R
R
R
R
[bit15 to bit0] OP15 to OP00: Compare value buffer bits
OP15 to OP00
Function
Compare value buffer
⋅
The output compare register is a 16-bit register to be used for comparison with the count value of the
16-bit free-run timer. Before enabling the operation of the 16-bit free-run timer, set a value in the output
compare buffer register (OCCPB).
⋅
When the value of the output compare register matches the count value of the 16-bit free-run timer, a
compare signal is generated and the output compare interrupt flag bit (IOP1: bit7 in the compare control
register (OCS)) is set. When the output level is set (OTD1: bit9 in the compare control register (OCS)),
the compare output level for the output compare register (OCCP) can be inverted.
⋅
When all the conditions listed below are met and a value that exceeds the peak value of the 16-bit
free-run timer is set to this register, the output compare output is "1" right after the buffer transfer. When
this register is set to "0000
H
", the output compare output is "0" right after the buffer transfer.
- The free-run timer is in up/down count mode.
- When the BUF bit in the compare control register (OCS) is "0" (buffer function enabled)
- When the BTS bit in the compare control register (OCS) is "1" (transfer when there is a
compare clear match)
- When the CMD bit in the compare control register (OCS) is "1"
- When the MOD bit in the compare mode control register (OCMOD) is "1"
When all the conditions listed above are not met, even if the value of this register matches the peak value of
the 16-bit free-run timer in up/down mode, no compare signal is generated.
The outcome is as follows according to the settings of the CMD bit in the compare control register (OCS).
- When the CMOD bit in the compare control register (OCS) is 1
When this register is set to "FFFF
H
", the output compare output is "1" regardless of the value of
the 16-bit free-run timer and the inversion mode.
When this register is set to "0000
H
", the output compare output is "0".
- When the CMOD bit in the compare control register (OCS) is 0
When this register is set to "FFFF
H
", the output compare output is "0" regardless of the value of
the 16-bit free-run timer and the inversion mode.
When this register is set to "0000
H
", the output compare output is "1".
Notes:
When accessing this register, use a half-word or word access instruction.
Do not use a read-modify-write instruction when accessing the compare register.
MB91520 Series
MN705-00010-1v0-E
966