Fujitsu FR81S User Manual
CHAPTER 25: 16-BIT OUTPUT COMPARE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 16-BIT OUTPUT COMPARE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
33
Case #5 where the free-run timer is in up/down count mode
⋅
The timing of data transfer from the compare buffer of the output compare is when there is a compare
clear match of the free-run timer.
⋅
The output compare output is reset to "0" upon a match in up count mode or set to "1" upon a match in
down count mode (CMOD: bit12=1 in OCS67).
⋅
The ch.0,1, ch.2,3 and ch.4,5 have the same operation.
Notes:
⋅
When the compare register value is set to "0000H", the output compare output is set to "0" when there
is a compare clear match of the free-run timer.
⋅
When the compare register value is set to a value greater than or equal to the compare clear register
value of the free-run timer, the output compare output is "1" when there is a compare clear match of the
free-run timer.
⋅
A comparison will be made and an interrupt flag occurs when there is a match between the compare
clear register value of the free-run timer and the compare register value of the output compare.
Figure 5-17 Case #5 Where the Free-run Timer Is in Up/Down Count Mode
CFFF
H
BFFF
H
0000
H
Count value
Time
Compare buffer
register
BFFF
H
Compare register
Compare output
initial value 0
CFFF
H
BFFF
H
BFFF
H
0000
H
FFFF
H
0000
H
CFFF
H
BFFF
H
0000
H
FFFF
H
Compare output
initial value 1
BFFF
H
MB91520 Series
MN705-00010-1v0-E
988