Fujitsu FR81S User Manual
CHAPTER 26: 16-BIT INPUT CAPTURE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : 16-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
9
4.1.2. Input Capture State Control Register : ICS
The bit configuration for the input capture state control register is shown below.
An input capture state control register (ICS) is used to select an edge, enable interrupt request, and control
an interrupt request flag. It is also used to indicate an effective edge detected by the input capture.
ICS01: Address 1280
H
(Access: Byte, Half-word, Word)
ICS23: Address 1288
H
(Access: Byte, Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
IEI1
IEI0
Initial value
0
0
0
0
0
0
0
0
Attribute
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R,WX
R,WX
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
Initial value
0
0
0
0
0
0
0
0
Attribute
R (RM1),
W
R (RM1),
W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit10] Reserved
Always write 0 to these bits.
[bit9] IEI1: Effective edge indication bit
IEI1
Function
0
A falling edge is detected.
1
A rising edge is detected.
⋅
This effective edge indication bit for the capture register (IPCP) indicates that a rising or falling edge has
been detected.
⋅
When a falling edge is detected, this bit is set to "0".
⋅
When a rising edge is detected, this bit is set to "1".
⋅
This bit is read-only.
Note:
If EG11, EG10: bit3, bit2 of the input capture state control register (ICS) are set to 00B, the value read from
this register is meaningless.
MB91520 Series
MN705-00010-1v0-E
998