Fujitsu FR81S User Manual
CHAPTER 26: 16-BIT INPUT CAPTURE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : 16-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
Notes:
⋅
If a read-modify-write (RMW) instruction is executed, "1" is always read.
⋅
If a software clear (write of "0") or a clear due to an interrupt clear signal ("H") and a hardware set
occur at the same time, the hardware set takes precedence.
[bit5] ICE1: Interrupt request enable bit
ICE1
Function
0
Interrupt request disabled
1
Interrupt request enabled
⋅
This bit is used to enable an input capture interrupt request for the input capture.
⋅
An input capture interrupt is generated when an interrupt request flag bit (ICP1: bit7) is set while this bit is
set to "1".
[bit4] ICE0: Interrupt request enable bit
ICE0
Function
0
Interrupt request disabled
1
Interrupt request enabled
⋅
This bit is used to enable an input capture interrupt request for the input capture.
⋅
An input capture interrupt is generated when an interrupt request flag bit (ICP0: bit6) is set while this bit is
set to "1".
[bit3, bit2] EG11, EG10: Edge selection bits
EG11
EG10
Function
0
0
No edge is detected (Stopped).
0
1
A rising edge is detected.
1
0
A falling edge is detected.
1
1
Both edges are detected.
⋅
These bits are used to specify an effective edge polarity of the external input for the input capture.
⋅
These bits are also used to enable the operation of input capture.
[bit1, bit0] EG01, EG00: Edge selection bits
EG01
EG00
Function
0
0
No edge is detected (Stopped).
0
1
A rising edge is detected.
1
0
A falling edge is detected.
1
1
Both edges are detected.
⋅
These bits are used to specify an effective edge polarity of the external input for the input capture.
⋅
These bits are also used to enable the operation of input capture.
MB91520 Series
MN705-00010-1v0-E
1000