Fujitsu FR81S User Manual
CHAPTER 27: UP/DOWN COUNTER
3. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : UP/DOWN COUNTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
6
3. Configuration
This section explains the configuration of the up/down counter.
Block Diagram of the Up/Down Counter
Figure 3-1 shows the block diagram of the up/down counter using ch.0 as an example.
Figure 3-1 Block Diagram of the Up/Down Counter
· Reload compare register (RCR)
This register sets reload and compare values of the up/down counter.
As shown below, this counter consists of upper 8 bits and lower 8 bits.
To use the register in 8-bit mode, use the lower side.
As shown below, this counter consists of upper 8 bits and lower 8 bits.
To use the register in 8-bit mode, use the lower side.
· Reload compare register upper (RCRH)
· Reload compare register lower (RCRL)
· Reload compare register lower (RCRL)
· Up/down count register (UDCR)
This register operates as the counter for the up/down counter.
As shown below, this counter consists of upper 8 bits and lower 8 bits.
To use the register in 8-bit mode, use the lower side.
As shown below, this counter consists of upper 8 bits and lower 8 bits.
To use the register in 8-bit mode, use the lower side.
· Up/down count register upper (UDCRH)
· Up/down count register lower (UDCRL)
· Up/down count register lower (UDCRL)
ZIN pin
Peripheral bus
CGE1
CTUT
CGSC
Edge/level detection
RCRL
Reload control
UCRE
RLDE
UDCC
CES1
CES0
CMS1
CMS0
AIN pin
BIN pin
Count
Clock selection
Prescaler
CLKS
CSTR
Count clock
UDF1
UDF0
CDCF
Interrupt output
UDFF
OVFF
CMPF
UDIE
CITE
CFIE
Counter
clear
CGE0
UDCRL
8-bit
8-bit
M16E
To upper byte
Carry
RCRL
: Reload compare register lower (RCCRL0, RCCRL1)
UDCRL
: Up/down count register lower (UDCRL0, UDCRL1)
PCLK
MB91520 Series
MN705-00010-1v0-E
1013