Fujitsu FR81S User Manual
CHAPTER 27: UP/DOWN COUNTER
3. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : UP/DOWN COUNTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
7
· Counter control register (CCR)
This register controls the up/down counter.
·
Counter status register (CSR)
This register checks the up/down counter status or controls an interrupt request.
· Count clock selection circuit
This circuit is used to select a count clock of the up/down counter.
· Prescaler
In using the up/down counter in the timer mode, this prescaler is used to select a division ratio of the
peripheral clock (PCLK).
peripheral clock (PCLK).
Clock
Table 3-2 lists the clocks used for the up/down counter.
Table 3-2 Clocks Used for the Up/Down Counter
Clock name
Description
Remarks
Operation clock
Peripheral clock (PCLK)
-
Count clock
Internal clock (peripheral clock)
Generated by dividing the peripheral
clock (PCLK)
clock (PCLK)
Counting of inputs from an external
pin
pin
Input from AIN and BIN pins
MB91520 Series
MN705-00010-1v0-E
1014