Fujitsu FR81S User Manual
CHAPTER 27: UP/DOWN COUNTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : UP/DOWN COUNTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
13
CMS1
CMS0
Operation mode
0
0
Timer mode
0
1
Up/down count mode
1
0
Phase difference count mode (multiply-by-2)
1
1
Phase difference count mode (multiply-by-4)
[bit9, bit8] CES1, CES0 :
Count clock edge selection bits
Select a detection edge of the AIN and BIN pins.
If the up/down count mode is selected, the signal is counted each time a signal edge selected by these bits is
detected.
detected.
CES1
CES0
Detection edge
0
0
Disables signal edge detection
0
1
Falling edge
1
0
Rising edge
1
1
Both edges
Note:
These bits are valid only if the up/down count mode has been set by the CMS1 and CMS0 bits (CMS1,
CMS0=01). This bit setting is ignored if another operating mode has been selected.
CMS0=01). This bit setting is ignored if another operating mode has been selected.
[bit7] Reserved bit
Write
This bit must always be written to "0".
Read
"0" is read.
[bit6] CTUT : Counter write bit
This bit transfers a value being set in the reload compare register (RCR) to the up/down count register
(UDCR).
(UDCR).
CTUT
Read
Write
0
"0" is read.
Ignored
1
The value is transferred.
MB91520 Series
MN705-00010-1v0-E
1020