Fujitsu FR81S User Manual
CHAPTER 27: UP/DOWN COUNTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : UP/DOWN COUNTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
15
[bit2] CGSC :
Counter clear/gate selection bit
This bit selects a function to be assigned to the ZIN pin as follows.
· Counter clear function
Clears the counter value to "0000
H
" when an effective edge signal is entered from the ZIN pin.
· Gate function
Operates the counter only when an effective level of signal is being entered from the ZIN pin.
Write value
Description
0
Counter clear function
1
Gate function
Note:
The ZIN pin functions if a combination of this bit and CGE1 and CGE0 bits is set.
Therefore, the CGE1 and CGE0 bits must always be set.
Therefore, the CGE1 and CGE0 bits must always be set.
[bit1, bit0] CGE1, CGE0 : Edge/level selection bits
These bits select an effective edge or an effective level of signal at the ZIN pin. The meaning of these bits
depends on the CGSC bit setting as follows.
depends on the CGSC bit setting as follows.
· If the counter clear function is selected by the CGSC bit (if CGSC=0)
An effective edge of signal is selected.
When a signal edge, selected by this bit, is detected at the ZIN pin, the counter value is cleared to
"0000
When a signal edge, selected by this bit, is detected at the ZIN pin, the counter value is cleared to
"0000
H
".
· If the gate function is selected by the CGSC bit (if CGSC=1)
An effective level of signal is selected.
The counter operates only when a signal having the level, selected by this bit, is being entered from the
ZIN pin.
The counter operates only when a signal having the level, selected by this bit, is being entered from the
ZIN pin.
CGE1 CGE0
If the counter clear function is
selected (CGSC=0)
If the gate function is selected
(CGSC=1)
0
0
Disables signal edge detection.
Disables signal level detection
(disabled counting)
0
1
Falling edge
"L" level
1
0
Rising edge
"H" level
1
1
Setting disabled
Setting disabled
MB91520 Series
MN705-00010-1v0-E
1022