Fujitsu FR81S User Manual
CHAPTER 27: UP/DOWN COUNTER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : UP/DOWN COUNTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
17
[bit5] UDIE :
Overflow/underflow interrupt enable bit
This bit sets whether or not to generate an overflow/underflow interrupt request when the up/down counter
overflows/underflows (OVFF/UDFF=1).
overflows/underflows (OVFF/UDFF=1).
Write value
Description
0
Disables overflow/underflow interrupt requests.
1
Enables overflow/underflow interrupt requests.
[bit4] CMPF :
Compare result match detection flag bit
This bit indicates that the counter value has matched the value set in the reload compare register (RCR).
When this bit is "1" and the CITE bit is set to "1", a compare result match interrupt request is generated.
When this bit is "1" and the CITE bit is set to "1", a compare result match interrupt request is generated.
CMPF
Read
Write
0
The value did not match.
This bit is cleared to "0".
1
The value matched.
Ignored
Note:
This bit changes to "1" in the following cases:
· The value matched in counting up.
· The value of the reload compare register (RCR) is reloaded to the counter.
· The value has already matched when the up/down counter is started.
· The value matched in counting up.
· The value of the reload compare register (RCR) is reloaded to the counter.
· The value has already matched when the up/down counter is started.
[bit3] OVFF :
Overflow detection flag bit
This bit indicates that the up/down counter has overflowed.
When this bit is "1" and the UDIE bit is set to "1", an overflow interrupt request is generated.
When this bit is "1" and the UDIE bit is set to "1", an overflow interrupt request is generated.
OVFF
Read
Write
0
No overflow has occurred.
This bit is cleared to "0".
1
An overflow has occurred.
Ignored
An overflow occurs if counting up is attempted when the counter value is "FFFF
H
".
MB91520 Series
MN705-00010-1v0-E
1024