Fujitsu FR81S User Manual
CHAPTER 30: POWER CONSUMPTION CONTROL
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : POWER CONSUMPTION CONTROL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
10
4.2. PMU Control Register : PMUCTLR (Power
Management Unit ConTroL register)
The bit configurations of the PMU control register are shown below.
This register controls PMU.
PMUCTLR : Address 0591
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SHDE Reserved IOCTMD IOCT
Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute R/W
R0,W0
R/W
R/W R0,W0 R0,W0 R0,W0 R0,W0
This register will be initialized by power-on reset, internal low-voltage reset, reset by simultaneous assert of
RSTX and NMIX, and hardware watchdog timer reset.
[bit7] SHDE (SHut Down Enable)
This setting is for whether you establish shutdown mode when the CPU mode transits to standby
(watch/stop).
SHDE
SHDE mode enable
0
When transiting to standby, you must not execute shutdown process.
1
When transiting to standby, you must execute shutdown process.
[bit6] Reserved
The read value is always "0". Be sure to write this bit to "0".
[bit5] IOCTMD (I/O Clear Timing MoDe)
This bit selects timing to maintain the I/O state when returning from standby (ShutDown) mode. (Hardware
process)
IOCTMD
I/O maintain cancellation request mode
0
I/O state is maintained until returning from standby (WATCH and STOP) mode.
1
I/O state is maintained until IOCT register is cleared.
[bit4] IOCT (I/O Clear Timing)
By setting this bit to “1” when IOCTMD=1, I/O state maintaining are cancelled.
IOCT
I/O maintain cancellation request
0
No request
1
Requesting
This register is cleared to "0" automatically after cancellation of I/O maintaining by I/O state maintaining
cancellation request is accepted.
Writing at times other than when I/O is maintained is invalid.
Writing this register to "0" is invalid.
[bit3 to bit0] Reserved
The read value is always "0". Be sure to write these bits to "0".
MB91520 Series
MN705-00010-1v0-E
1097