Fujitsu FR81S User Manual
CHAPTER 31: LOW-VOLTAGE DETECTION (INTERNAL
LOW-VOLTAGE DETECTION)
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
INTERNAL LOW-VOLTAGE DETECTION (INTERNAL POWER SUPPLY
LOW-VOLTAGE
DETECTION)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
7
4.1. Internal Low-Voltage Detection Register : LVD
(Low-Voltage Detect internal power fall register)
The bit configuration of the internal low-voltage detection register is shown.
This register has the internal low-voltage detection flag (LVD_F).
LVD : Address 0586
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
LVD_PD
LVD_SEL[2:0]
LVD_OE
Reserved
LVD_F
Initial value
0
1
0
0
0
0
0
0
Attribute
R/W
R/W1
R/W0
R/W0
R/W
R0,WX R0,WX R(RM1), W
[bit7] LVD_PD (Low Voltage Detect fall Power Down)
This bit is used in order to set whether a fall of the internal power supply voltage in the device should be
detected or not.
LVD_PD
Setting for detection of internal power
supply voltage fall power down in the
device
0
Disabled (Detection is executed.)
1
Enabled (Detection is stopped.)
*This bit is initialized by only power-on reset.
Note:
Set detection enable (OE = 0) after 100 μs, if this bit sets the status of power-down enable to disable
(operation start). If set it before 100 μs, some detection flag setting will be occur.
[bit6 to bit4] LVD_SEL[2:0] (Low Voltage Detect power fall SELect)
These bits select the detection level of a fall of the internal power supply voltage.
LVD_SEL[2:0]
Setting for detection level of fall of internal power
supply voltage
100
0.9V ± 0.1V
Other than those above
Setting is prohibited
*These bits can be rewritten only when LVD_OE="1".
MB91520 Series
MN705-00010-1v0-E
1148