Fujitsu FR81S User Manual
CHAPTER 34: CLOCK SUPERVISOR
3. Register
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK SUPERVISOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
8
[bit2] SSVE (Sub clock SuperVisor Enable) : Sub clock supervisor enable
When this bit is set to "1", the sub clock supervisor is enabled. If this bit is set to "1", the CR oscillator
needs to have oscillation stabilization wait time for 20μs or more.
This bit is only initialized to "1" when the power is turned on.
Other types of resets have no effect on this bit.
This bit will be invalid when the single clock product is set to operate in the sub clock mode (SCKS=1,
CSELR:SCEN=1).
SSVE
Description
0
Sub clock supervisor disabled
1
Sub clock supervisor enabled (Initial value)
[bit1] Reserved
"0" should be written to this bit.
[bit0] Reserved
"0" should be written to this bit.
MB91520 Series
MN705-00010-1v0-E
1181