Fujitsu FR81S User Manual
CHAPTER 34: CLOCK SUPERVISOR
4. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK SUPERVISOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
10
4.1. Initial State
This section explains the initial state.
When initial setting, the oscillation of the CR oscillator, main clock supervisor function, and sub clock
supervisor function have been enabled.
CR Oscillator
The oscillation is enabled when the power is turned on.
Only when changing to the standby mode with "0" written in oscillation enable bit (CSVCR:RCE) at the
standby mode, it stops. When the standby mode is made clear, the oscillation is automatically restarted.
Main Clock Supervisor
Main clock supervisor is enabled after the main oscillation stabilization wait time has elapsed.
When the main clock supervisor is enabled, if the main clock stops, the main clock is replaced by the CR
oscillation clock.
Moreover, the MM bit of the CSVCR register is set to "1" and an RST level reset is generated.
[Notes]
Because the main oscillation stabilization wait time is measured by the main clock itself, if the main clock
stops before the oscillation stabilization wait time has elapsed, the main oscillation stabilization wait time
does not end and the main clock supervisor is not enabled.
In this case, after the timeout time measured by the internal CR oscillator has elapsed, the main supervisor
function is enabled regardless of the oscillation stabilization wait time and the main clock stop is detected.
Sub Clock Supervisor
After the timeout period measured by internal CR oscillator passes, it is enabled.
Behavior when a sub-clock stops when the sub-clock supervisor has been permitted changes according to
whether MCU operates with the main clock or it operates with a sub-clock.
・
For the main clock mode
When a sub clock stops while operating in the main clock mode, a sub clock replaces two dividing
frequency of the CR oscillation clock. Afterwards, reset keeps being not generated and operating in the
main clock mode though the SM bit of the CSVCR register is set to "1".
Under such a condition, clock changes to the sub-clock mode that operates with the CR oscillation clock
when changing to the sub-clock mode.
・
For the sub clock mode
When a sub clock stops while operating in the sub-clock mode, two dividing frequency of the CR
oscillation clock replaces a sub clock. Afterwards, the SM bit of the CSVCR register is set to "1", and
reset of the RST level is generated.
MB91520 Series
MN705-00010-1v0-E
1183