Fujitsu FR81S User Manual
CHAPTER 34: CLOCK SUPERVISOR
4. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK SUPERVISOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
17
4.8. Return from CR Clock
Return from the CR clock is shown.
Main Clock Supervisor
The main clock stops when the CPU detects that the MM bit has been set after recovering from a reset, and
it can be judged that these has been a change in the CR oscillation clock. At this time, it is possible to return
to the main clock by writing "0" in the MM bit if it can be confirmed that the main clock is restored.
When the main clock is not restored, writing "0" in the MM bit does not have any influence. The MM bit
keeps maintaining "1".
The MM bit is cleared when the main clock works when "0" is written in the MM bit, and the clock returns
to the main clock via a synchronous stage.
It can perform polling on the MM bit until the main clock is restored.
ldi #_csvcr,r1
clear_CSV_loop:
bandh #0b1001,@r1 ;; Clear MM+SM
btsth #0b0110,@r1 ;; Check: Is one of them 1?
bne clear_CSV_loop
Note:
Set "0" to PMUCTLR.SHDE to return to the main clock.
Sub Clock Supervisor
A sub clock stops when the CPU detects that the SM bit has been set and it can be judged that there has
been a change in the CR oscillation clock. At this time, it is possible to return to the sub clock by writing
"0" in the SM bit if it can be confirmed that the sub clock is restored.
When a sub clock is not restored, writing "0" in the SM bit does not have any influence. The SM bit keeps
maintaining "1".
The SM bit is cleared when a sub clock works when "0" is written in the SM bit, and the clock returns to a
sub clock via a synchronous stage.
It can perform polling on the SM bit until a sub-clock is restored. (The same method as main clock
supervisor can be used.)
Note:
Set "0" to PMUCTLR.SHDE to return to the sub clock.
MB91520 Series
MN705-00010-1v0-E
1190