Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
2. Features
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
4
2. Features
This section explains the features of the external bus interface.
· Address up to 22 bits long (4 MByte space) can be output. (The address space can be extended to 8
MByte by treating the lowermost bit as fixed and extending the upper bit by 1 bit, depending on setting
the ACR0 to ACR3:ADTY bit.)
· Supports split address/data bus
•
Able to connect to asynchronous memory
· Supports multiplexed address/data bus
· Four independent chip select areas (called CS areas below) can be configured, and chip select output
corresponding to each area can be performed
· The size of each CS area can be selected from 16 options in the range of 64 KByte to 4 MByte
· Each CS area can be set to an arbitrary position within the external bus area
· The following functions can be set independently for each CS area
•
Enabled or disabled
•
Data bus width (8-bit or 16-bit)
•
Write prohibited (read-only) setting
•
Byte order
•
CS0 area : Big endian
•
Not CS0 area : Supports big and little endian
•
Address shift output mode
· Bus type selectable for each CS area
· Split address/data bus
· Multiplexed address/data bus
· Type 0 (byte write strobe signal output)
· The following timings are configurable for each CS area
•
Common to read/write access
•
Address -> CS signal setup cycle count
•
Address strobe signal output cycle count
•
Extend read/write bus cycle by external ready input
•
Read access
•
Read access automatic wait
•
CS signal → Read strobe signal setup cycle count
•
Read strobe signal → CS signal hold cycle count
•
Read access → Insert idle cycle between write accesses
•
Write access
•
Write access automatic wait
•
CS signal → Write strobe signal setup cycle count
•
Write strobe signal → CS signal hold cycle count
· Insert write recovery cycles
•
Multiplexed address/data bus
•
Address output cycle count
MB91520 Series
MN705-00010-1v0-E
1203