Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
24
5.2.2. Address/Data split bus write protocol
This section shows the protocol for write access using an address/data split bus.
Figure 5-2 Address/data split bus (Write operation example)
Operating example description
cycle1 :
"L" is output to ASX for 1 cycle to indicate that access is starting from this cycle. A00 to A21
indicate the address information of the access destination for this cycle.
cycle2 :
After the configured count has finished from when the access was started, "L" is output to CSnX
(n=0 to 3). CSnX continues to output "L" until the access is complete. Devices on the external bus need to
execute processing for the access only within the period where CSnX="L".
cycle3 :
After the configured count has finished after "L" starts being output to CSnX, "L" is output to
WRnX (n=0, 1). External bus devices are required to fetch the value of D16 to D31 within the write strobe
period where "L" is output to WRnX.
cycle4 :
After the configured count has finished from when WRnX="L" starts being output, the output of
WRnX returns to "H" and the write strobe period ends. In this example, the write strobe period is extended
by 1 cycle. At the end of this cycle, the output of WRnX returns to "H" and the strobe period ends.
cycle5 :
The output of CSnX returns to "H" after the configured count finishes from when WRnX returns to
"H", and the write access finishes. In this example, CSnX returns to "H" when this cycle ends and the write
access finishes.
Signal description
External bus output signals are synchronized to the rising edge of SYSCLK.
cycle no.
7
0
6
5
4
3
2
1
A0
D0
SYSCLK
ASX
CSnX
(n=0,1,2,3)
WRnX
(n=0,1)
Dxx
A00 to A21
H: Dxx is input
L: Dxx is output
L: Dxx is output
MB91520 Series
MN705-00010-1v0-E
1223