Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
31
5.5. Data Alignment
This section shows the data alignment.
Each CS area supports both big endian and little endian. However, CS0 only supports big endian. The data
bus width can be selected between 8-bit and 16-bit for each CS area.
The following shows the data alignment for the external access size and the corresponding control signals
for each endian setting and data bus width setting.
Table 5-3 Big endian - 16 bits
Access
Split
access
Output pins
Size
Address
lowermost
2 bits
A01, A00 D31 to D24 D23 to D16 WR0X WR1X
Byte
00
-
00
bit7 to bit0
○
01
-
01
bit7 to bit0
○
10
-
10
bit7 to bit0
○
11
-
11
bit7 to bit0
○
Half-word
0n
-
00
bit15 to bit8 bit7 to bit0
○
○
1n
-
10
bit15 to bit8 bit7 to bit0
○
○
Word
nn
First split
access
00
bit31 to
bit24
bit23 to
bit16
○
○
Second split
access
10
bit15 to bit8 bit7 to bit0
○
○
Table 5-4 Big endian - 8 bits
Access
Split
access
Output pins
Size
Address
lowermost
2 bits
A01, A00
D31 to D24
D23 to
D16
WR0X WR1X
Byte
00
-
00
bit7 to bit0
-
○
-
01
-
01
bit7 to bit0
-
○
-
10
-
10
bit7 to bit0
-
○
-
11
-
11
bit7 to bit0
-
○
-
MB91520 Series
MN705-00010-1v0-E
1230