Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
34
5.6. Address Information
This section shows the address information.
5.6.1. Address information and output pins
· Split address/data bus
22-bit address information is output to A00 to A21.
· Multiplexed address/data bus
In the address/data multiplexed bus, the address information is output to data bus pins D16 to D31
during the address output cycle. The address bit width that can be output is determined by the data bus
width setting. Even while address/data multiplexed bus is selected, the address is output to address pins
A00 to A21. The missing parts of address information output to pins D16 to D31 can be supplemented
by using address pins A00 to A21.
5.6.2. Address type
The output of address information can be selected from normal type that outputs as normal and the shift
type that outputs using bit shift. This is set using ACR:ADTY.
· ADTY=0
The normal output mode. The address information is output directly to the pins without bit shifting.
· ADTY=1
Address shift output mode. The address bus information is output to the pins after bit shifting.
The relationship between the address type (ACR:ADTY), bus type (ACR:BSTY), bus width, output address
information, and address output pins is as follows.
Table 5-7 Output address and output pins
ACR register
Bus
width
[bit]
A21 to A00
Output pins D31 to D16 during address output cycle
ADTY BSTY
D31 to D24
D23 to D16
0
0
8
Address[21:0]
-
-
16
0
1
8
Address[21:0]
Address[7:0]
-
16
Address[21:0]
Address[15:8]
Address[7:0]
1
0
8
Address[21:0]
-
-
16
Address[22:1]
1
1
8
Address[21:0]
Address[7:0]
-
16
Address[22:1]
Address[16:9]
Address[8:1]
MB91520 Series
MN705-00010-1v0-E
1233