Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
38
Address/Data multiplexed bus timing parameters
This section shows the timing parameters that can be configured in the address/data multiplexed bus.
Figure 5-7 Address/Data Multiplexed Bus Timing Parameters
A
S
C
Y
0
1
0
3
0
3
0
3
0
1
5
0
15
0
3
0
3
0
3
SY
S
CL
K
AS
X
D
x
x
W
R
nX
(n=0,1
)
R
DX
CSnX
(
n
=
0
,
1
,2,3)
0
3
*1 :
During write access, the write data of Dxx is output immediately after the address output cycle ends.
*2 :
The valid value output of Dxx is extended by the number of cycles specified by WRCS during write access.
AC
S
[1:0
]
CSRD[1:0]
R
IDL[1:0]
or
WRCV[1:0
]
R
DCS[
1
:0
]
RWT[3:0]
WWT[3:0]
WRCS[1:0]
data
A
D
CY
[
1
:
0
]
address
CSWR[1:0]
*1
*2
H: Dxx is input
L: Dxx is output
L: Dxx is output
MB91520 Series
MN705-00010-1v0-E
1237