Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
39
Table 5-9 Address/Data multiplexed bus timing parameters
Parameter name
Function name
Description
ASCY(ASX CYcle)
ASX output extension
cycle count
"L" is output to ASX for (ASCY+1) cycles from when
the access starts.
ACS[1:0]
(A00 to A21 to CSnX delay
cycle)
A00 to A21 → CSnX
delay cycle count
Output of "L" to CSnX (n=0 to 3) starts after the ACS
count has finished from ASX output.
ADCY[1:0](ADdress CYcle)
Address output
extension cycle count
If ADCY
≥
ASCY
D16 to D31 output (ADCY+1) cycle address information
from when access starts. During writes, write data is
output after the count finishes until the access finishes.
If ADCY < ASCY
The count value is changed from (ADCY+1) to
from when access starts. During writes, write data is
output after the count finishes until the access finishes.
If ADCY < ASCY
The count value is changed from (ADCY+1) to
(ASCY+1).
There are no other differences.
The ADCY count operates independently of the other
There are no other differences.
The ADCY count operates independently of the other
counters. Furthermore, it is not affected by the start
conditions of other counters. As a result, there are no
limits on setting the counter value in order for the overall
protocol to function correctly. See the prohibited setting
conditions outside of the table.
CSRD[1:0]
(CSnX to RDX setup cycle)
CSnX → RDX
setup cycle
During read access, output of "L" to RDX begins after
the CSRD count finishes after "L" output to CSnX
begins.
RWT[3:0]
(Read access auto WaiT)
Read access
auto wait
During read access, the RDX output returns to "H" after
(RWT+1) count from when output of "L" to RDX begins.
RDCS[1:0]
(RDX to CSnX hold cycle)
RDX → CSnX
hold cycle
During read access, the output of CSnX returns to "H"
after RDCS count from the cycle where the output of
RDX returns to "H".
CSWR[1:0]
(CSnX to WRnX setup cycle)
CSnX → WRnX
setup cycle
During write access, output of "L" to WRnX (n=0, 1)
begins after the CSWR count finishes after "L" output to
CSnX begins.
WWT[3:0]
(Write access auto WaiT)
Write access
auto wait
During write access, the output to WRnX returns to "H"
after (WWT+1) count finishes.
WRCS[1:0]
(WRnX to CSnX hold cycle)
WRnX → CSnX
hold cycle
During write access, the output of CSnX returns to "H"
after WRCS count from the cycle where the output of
WRnX returns to "H".
RIDL[1:0]
(Read access IDLe cycle)
Read access
idle cycle
After a read access has finished, the next access is able to
start after RIDL count has finished.
WRCV[1:0]
(Write ReCoVery cycle)
Write recovery cycle
After a write access has finished, the next access is able
to start after WRCV count has finished.
The number of access cycles is determined from the following formula.
Number of read access cycles = Address output(1) + ACS(0 to 3) + CSRD(0 to3) + Data output(1) +
RWT(0 to 15) + RDCS(0 to 3)
Minimum: 2 cycles; Maximum: 26 cycles
MB91520 Series
MN705-00010-1v0-E
1238