Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
45
Table 5-10 List of parameter
Parameter name
Description
RWT[3:0]
Sets the auto wait cycle count during the read access cycle.
This is configured when you want to extend the read access cycle.
This is configured when you want to extend the read access cycle.
WWT[3:0]
Sets the auto wait cycle count during the write access cycle.
This is configured when you want to extend the write access cycle.
RIDL[1:0]
Sets the idle cycle count after the read access.
RIDL is configured in order to prevent conflicts on the data bus between the read data
from a device with a long output off time and the data of the subsequent access.
RIDL is configured in order to prevent conflicts on the data bus between the read data
from a device with a long output off time and the data of the subsequent access.
WRCV[1:0]
Sets the write recovery cycle count.
This is configured to control access to devices that have limits on the interval when
performing an access after a write access.
This is configured to control access to devices that have limits on the interval when
performing an access after a write access.
CSRD[1:0]
Sets the number of cycles after CSnX (n=0 to 3) is asserted until RDX is asserted.
This is configured if setup time is required for asserting CSnX when RDX is asserted
during read access.
This is configured if setup time is required for asserting CSnX when RDX is asserted
during read access.
RDCS[1:0]
Sets the number of cycles after RDX is negated until CSnX (n=0 to 3) is negated.
This is configured if hold time is required for the negation of CSnX after RDX is
negated during read access.
This is configured if hold time is required for the negation of CSnX after RDX is
negated during read access.
CSWR[1:0]
Sets the number of cycles after CSnX is asserted until WRnX (n=0, 1) is asserted.
This is configured if setup time is required for asserting CSnX when WRnX is asserted
during write access.
This is configured if setup time is required for asserting CSnX when WRnX is asserted
during write access.
WRCS[1:0]
Sets the number of cycles after WRnX is negated until CSnX is negated.
This is configured if hold time is required for the negation of CSnX after WRnX is
negated during write access.
This is configured if hold time is required for the negation of CSnX after WRnX is
negated during write access.
ADCY[1:0]
Sets the number of cycles to extend address output to the data bus while address/data
multiplexed bus is selected. Even if ADCY is set to "00", if ASCY is set to "1" then the
address output cycle is extended by 1 cycle. Set this to"00" when the address/data split
bus is selected.
multiplexed bus is selected. Even if ADCY is set to "00", if ASCY is set to "1" then the
address output cycle is extended by 1 cycle. Set this to"00" when the address/data split
bus is selected.
ACS[1:0]
Sets the number of delay cycles from outputting A00 to A21 and ASX to outputting
CSnX. This is used when the address for CSnX assert needs setup time, or when CSnX
edges are required when accessing the same chip select area in sequence.
CSnX. This is used when the address for CSnX assert needs setup time, or when CSnX
edges are required when accessing the same chip select area in sequence.
ASCY
Sets the number of ASX assert extensions cycles.
RDYE
Sets whether the wait insertion function by external RDY pin is enabled or disabled.
Setting ASR
The following settings are made using ASR.
1.
Configure the CS areas.
2.
Select whether writes are enabled or disabled.
3.
Select the byte ordering.
4. Enable the CS.
MB91520 Series
MN705-00010-1v0-E
1244