Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
47
The size of the CS area and the setting of ASZ and SADR
The size of the CS area
ASZ[3:0]
The valid SADR bit
64KB
0000
SADR[31:16]
128KB
0001
SADR[31:17]
256KB
0010
SADR[31:18]
512KB
0011
SADR[31:19]
1MB
0100
SADR[31:20]
2MB
0101
SADR[31:21]
4MB
0110
SADR[31:22]
8MB
0111
SADR[31:23]
16MB
1000
SADR[31:24]
32MB
1001
SADR[31:25]
64MB
1010
SADR[31:26]
128MB
1011
SADR[31:27]
256MB
1100
SADR[31:28]
512MB
1101
SADR[31:29]
1GB
1110
SADR[31:30]
2GB(initial value of ASR0)
1111
SADR[31]
Note:
Arrange each of the CS areas such that they do not overlap. Operation is not guaranteed if the CS areas
are overlapping.
An example of the values set in SADR and ASZ and the actually allocated CS areas is shown below.
Setting example
• CS0 settings
ASR0:ASZ[3:0]=0010
ASR0:SADR[31:16]=0x000C
→ 0x000C0000 to 0x000FFFFF becomes the CS0 area.
• CS1 settings
ASR1:ASZ[3:0]=0000
ASR1:SADR[31:16]=0x0006
→ 0x00060000 to 0x0006FFFF becomes the CS1 area.
MB91520 Series
MN705-00010-1v0-E
1246