Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
49
Figure 5-12 CS1 Settings Sample Program
16bi
t
RW
T
WW
T
RID
L
WRC
V
CSR
D
RDC
S
CSW
R
WRC
S
ADC
Y
AC
S
ASC
Y
RDY
E
_
d
isable
_
CS
0
ld
i
#_AS
R
0,
r0
ld
0x0,
r
1
s
t
r1,
@r0
_set
_
AC
R
1
ld
i
#_AC
R
0,
r0
ld
i
#0x40,
r
1
s
t
r1,
@r0
_set
_
A
WR
1
ld
i
#
_
A
WR
1
,
r0
ld
i
#0x034b5a00
r
1
s
t
r1,
@r0
_set
_
AS
R
1
ld
i
#_AS
R
1,
r0
ld
i
#0x00400005
r1
s
t
r1,
@r0
l
d
@r0,
r2
cm
p
r1,
r2
ACR1 Setting Example
Shows the setting values for the following table.
ASR1 Setting Example
•
CS1 area size : 64Kbyte
•
CS1 area address: 0x0040_0000 to 0x0040_FFFF
•
Write enable
•
Big endain
•
CS1 valid
Program Example
AWR1 Setting Example
Shows the setting values for the following table.
AWR1 setting value : 0x034b5a00
3 cycles
4 cycles
2 cycles
3 cycles
1 cycle
Write type 0
Address/data multiplexed bus
//#
_ASR0 is the ASR0 address value
// #_ACR1 is the ACR1 address value
// Set ACR1 to 0x40
// #_AWR1 is the AWR1 address value
// Set AWR1 to 0x034b5a00
// Check the setting value of ASR1
// #_ASR1 is the ASR1 address value
// Set ASR0 to 0x00400005
ASR1 setting value : 0x00400005
Bus type
Data bus width
Address output type
Write signal type
1 cycle
2 cycles
2 cycles
0 cycle
0 cycle
Invalid
Normal
Address/data multiplexed bus setting
Bits other than the above setting bits are Reserved and are set to 0.
ACR1 setting value : 0x40
:
Bits other than the above setting bits are Reserved and are set to 0.
MB91520 Series
MN705-00010-1v0-E
1248