Fujitsu FR81S User Manual

CHAPTER 39: RAMECC

3. Configuration

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : RAMECC

FUJITSU SEMICONDUCTOR CONFIDENTIAL

3. Configuration

This section shows the configuration of the RAMECC.

Figure 3-1 Block Diagram of XBS RAM ECC Function (Configuration)

Figure 3-2 Block Diagram of Backup-RAM ECC Function (Configuration)

False error data generation

EFEARA (ECC false error generation register)

FERR

EI[7:0]

EY[7:0]

ECC code generation

Data [31:0] ECC code [19:0]

Write data
Data [31:0]

Read data
Data [31:0]

EFECRA

(ECC error control register)

False error write selection signal

False error data [51:0]

RAM write data [51:0]

with ECC code

RAM write data
with ECC code

RAM read data
with ECC code

RAM double-bit error interrupt

ECC code check

Data [31:0] (*1) Data [31:0]

ECC code [19:0]

EEARA( ECC error register)

DEI

DEIE

Double-bit
error detection

EECSRA

(ECC error control
register)

1: In case of single-bit error de

corrected data is output

[31:0]

[51:32]

[31:0]

[51:32]

False error data generation

EFEARX (ECC false error generation register)

FERR

EI[7:0]

EY[7:0]

ECC code generation

Data [31:0] ECC code [19:0]

Write data
Data [31:0]

Read data
Data [31:0]

EFECRX

(ECC error control register)

False error write selection signal

False error data [51:0]

RAM write data [51:0]

with ECC code

RAM write data
with ECC code

RAM read data
with ECC code

RAM double-bit error interrupt

ECC code check

Data [31:0] (*1) Data [31:0]

ECC code [19:0]

EEARX( ECC error register)

DEI

DEIE

Double-bit
error detection

EECSRX

(ECC error control
register)

1: In case of single-bit error de

corrected data is output

[31:0]

[51:32]

[31:0]

[51:32]

*1: In case of single-bit error detection,

corrected data is output.

*1: In case of single-bit error detection,

corrected data is output.

MB91520 Series

MN705-00010-1v0-E

1296