Fujitsu FR81S User Manual
CHAPTER 39: RAMECC
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAMECC
FUJITSU SEMICONDUCTOR CONFIDENTIAL
20
5.1. RAMECC Function
The RAMECC function is explained.
The RAMECC always functions (It, however, stops at RAM diagnosis). When an error is detected, the
address where the error occurred is hold in the register EEAR. If another error is detected while the
previous address is being held in the register EEAR, the EEAR register will not be overwritten. Thus the
previous address is maintained.
ECC sign matrix records redundant five bits as ECC code by byte units.
RAM_DATA
[51:0]
[7:0]
[15:8]
[23:16]
[31:24] [36:32] [41:37]
[46:42]
[51:47]
DATA[31:0]
DATA
[7:0]
DATA
[15:8]
DATA
[23:16]
DATA
[31:24]
ECC
[4:0]
ECC
[9:5]
ECC
[14:10]
ECC
[19:15]
Flow chart of the operation is shown below.
Read request
ECC test execution
No error?
Read
Record address in the
EEAR
Single-bit
error?
1-bit error correction
Read
2-bit error detection
Read
EECSR.
DEI=1?
RAM double-bit error
interrupt request
occurrence
Interrupt request does
not occur
Yes
No
Yes
Yes
No
No
MB91520 Series
MN705-00010-1v0-E
1311