Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
2. Features
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
8
Assist Mode
LIN-UART (LIN Communication Control UART) provides specific functions to support LIN bus.
Automatic transmission/automatic detection of the header in the LIN communication is possible. It is also
equipped with the FIFO for transmission/reception (64 bytes each).
Item
Function
Data buffer
⋅
Full-duplex double buffering (when FIFO is unused)
⋅
Transmission/reception FIFO (64 bytes each) (when FIFO is used)
Serial input
Execute over-sampling for three times by the bus clock and determine the reception
value by the majority of the sampling value.
Transfer mode
Asynchronous
Baud rate
⋅
Dedicated baud rate generator provided (comprising of 15-bit reload counter)
⋅
External clock input can be adjusted by the reload counter
⋅
Automatic baud rate adjustment with Sync Field reception
Data length
9 bits
Signaling system NRZ (Non Return to Zero)
Start Bit Detection Synchronize with the start bit falling edge
Reception error
detection
<The error is detected by the self-check of the transmission side>
⋅
LIN bus error
<The error is detected by the self-check of the transmission side and by the reception
side >
⋅
Framing error
⋅
Overrun error
⋅
LIN ID parity error
⋅
LIN checksum error
<The error is detected by the reception side of the automatic baud rate adjustment
prohibition>
⋅
LIN Sync Data error
Interrupt request
⋅
Transmission interrupt
(1) Data transmission interrupt (Transmission data empty, transmission bus idle)
(2) Transmission FIFO interrupt (When transmission FIFO is the interrupt threshold or
less, or transmission FIFO is empty).
⋅
Reception interrupt
(1) Data reception interrupt (Reception completed)
(2) Reception FIFO interrupt (When reception FIFO is the interrupt threshold or
more).
(3) Various error interrupts (LIN bus error, LIN ID parity error, LIN Sync Data error,
LIN ID parity error, framing error, overrun error, and LIN checksum error)
⋅
Status interrupt
(1) Automatic header completion interrupt
(2) Sync Field detection interrupt
(3) Checksum arithmetic operation completion interrupt
⋅
Both transmission and reception employ extended intelligent I/O service (EI
2
OS)
and DMA function
Timer feature
⋅
Employs 16-bit serial timer
⋅
Dividing ratio of operating clock is selectable (1/1 to 1/256)
⋅
External trigger available
LIN bus option
⋅
LIN protocol revision 2.1 is supported.
⋅
Master device operation
⋅
Slave device operation
⋅
LIN Break field generation (can be changed to 13 to 16 bits)
⋅
LIN Break Delimiter generation (can be changed to 1 to 4 bits)
⋅
LIN Break field detection
⋅
Detection of start/stop edges for LIN synch field connected to input capture by input
capture (See Section "CHAPTER: INPUT CAPTURE".)
MB91520 Series
MN705-00010-1v0-E
1321