Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
22
4.1.2.
FIFO Control Register 1: FCR1
FIFO control register (FCR1) is used for the test settings of FIFO, selection of transmission/reception FIFO,
settings of transmission FIFO interrupt enable, and control of interrupt flag.
FCR1n(n=1 to 11): Address Base addr + 20
H
(Access: Byte, Half-word, Word)
7
6
5
4
3
2
1
0
bit
Reserved
-
FLSTE
FRIIE
FDRQ
FTIE
FSEL
0
0
-
0
0
1
0
0
Initial value
R/W0
R/W0 R0,WX
R/W
R/W R(RM1),
W
R/W
R/W
Attribute
[bit7, bit6] Reserved
These bits must always be written to "0".
[bit5] Undefined
Always reads "0". No effect for writing operations.
[bit4] FLSTE (Flag for data LoST detection Enable): Retransmission data lost detection enable bit
This bit enables FIFO retransmission data lost flag (FLST) detection.
When this bit is set to "0": FLST bit detection disabled
When this bit is set to "1": FLST bit detection enabled
Note:
When this bit is set to "1", set this bit to "1" after setting "1" to the FSET bit.
[bit3] FRIIE (Flag for Receive FIFO IdlE detection Enable): Reception FIFO idle detection enable bit
This bit configures whether or not to detect the reception idle state for 8-bit time or longer while the
reception FIFO contains valid data. When reception interrupts are enabled (SCR:RIE=1), a reception
interrupt will be generated once it detects reception idle state.
When this bit is set to "0": Reception idle state detection disabled
When this bit is set to "1": Reception idle state detection enabled
[bit2] FDRQ (transmit FIFO Data ReQuest): Transmission FIFO data request bit
It is a data request bit for transmission FIFO. When this bit is set to "1", it indicates that transmission data is
being requested. When transmission FIFO interrupts are enabled (FTIE=1) at this time, a FIFO transmission
interrupt request will be output.
FDRQ set condition
⋅
When the transmission FIFO interrupt control no used.
⋅
FBYTE (for transmission) = 0 (transmission FIFO is empty)
⋅
The transmission FIFO reset.
⋅
When the transmission FIFO interrupt control is used.
⋅
FTICR setting value ≥ FTICR reading value (The storage data value of the transmission FIFO is the
interrupt trigger level or less.)
⋅
The transmission FIFO reset.
FDRQ reset condition
⋅
Writing "0" to this bit.
⋅
If the transmission FIFO becomes full.
MB91520 Series
MN705-00010-1v0-E
1335