Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
25
[bit3] FCL2 (FIFO Clear 2): FIFO2 reset bit
This bit resets FIFO2.
When this bit is set to "1", it initializes the internal state of FIFO2.
Only the FCR1:FLST bit will be initialized while other bits of FCR1/0 register are retained.
Notes:
⋅
Execute FIFO2 reset after disabling transmission/reception.
⋅
Execute after clearing the transmission FIFO interrupt enable bit to "0".
⋅
Valid data count of FBYTE2 register will be "0".
[bit2] FCL1 (FIFO Clear 1): FIFO1 reset bit
This bit resets FIFO1.
When this bit is set to "1", it initializes the internal state of FIFO1.
Only the FCR1:FLST bit will be initialized while other bits of FCR1/0 register are retained.
Notes:
⋅
Execute FIFO1 reset after disabling transmission/reception.
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Execute after clearing the transmission FIFO interrupt enable bit to "0".
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Valid data count of FBYTE1 register will be "0".
[bit1] FE2 (FIFO Enable 2): FIFO2 operation enable bit
This bit enables/disables operation of FIFO2.
⋅
To use FIFO2, set this bit to "1".
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When this bit is selected as reception FIFO by the FSEL bit, this bit is cleared to "0" if a reception error
occurs. As long as the reception error is not cleared, you will not be able to set this bit to "1".
⋅
When the transmission FIFO is used, if the transmission buffer is empty (SSR:TDRE="1"), or when the
reception FIFO is used, if the reception buffer is empty (SSR:RDRF="0"), set "1" or "0" to this bit.
⋅
Even if you have FIFO2 disabled, the state of FIFO2 will be retained.
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[UART] [CSIO] When any data is present in FIFO2 and UART is enabled for transmission
(SCR:TXE=1) after FIFO2 is set for transmission FIFO (FCR1:FSEL=1) and this bit is set to “1”,
transmission will immediately be started. In this case, after SCR:TIE bit and SCR:TBIE bit are set to “0”,
set “1” to this bit, SCR:TIE bit and SCR:TBIE bit.
⋅
[CSIO] When you use as a reception FIFO, after reception is disabled (SCR:RXE=0), set this bit to “0”
when reception buffer is empty (SSR:RDRF=“0”) and no valid data is present in the reception FIFO
(FBYTE2=0).
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[CSIO] When you use as a reception FIFO, after reception is disabled (SCR:RXE=0), set this bit to “1”
when reception buffer is empty (SSR:RDRF=“0”).
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[LIN-UART] When FIFO2 is set for transmission FIFO, this bit is set to “1” while any data is present in
FIFO2 and LIN interface (v2.1) transmission is enabled (TXE=1), transmission will immediately be
started. In this case, after TIE bit and TBIE bit are set to “0”, set “1” to this bit, TIE bit and TBIE bit.
Notes:
[I
2
C]
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Changes to enable or disable must be made while IBSR:BB bit is “0” or IBCR:INT bit is “1”.
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When selected as a reception FIFO to detect reservation address and operate as a slave transmission, set
this bit to “0” with reservation address detection interrupt and set IBCR:ACKE=“0”.
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When SSR:RDRF bit is “1” while using as a reception FIFO and this bit is changed from “1” to “0”, the
reception FIFO will not be disabled until SSR:RDRF bit becomes “0”.
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When any data is present in FIFO2 while using as a transmission FIFO and this bit is changed from “0”
to “1”, set this bit to “1” after SMR:TIE bit is set “0” and set SMR:TIE bit to "1".
MB91520 Series
MN705-00010-1v0-E
1338