Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
28
Notes:
⋅
[UART] [LIN-UART] Set FBYTE register of the transmission FIFO to "8’h00".
⋅
[UART] Disable reception before making any change.
⋅
[CSIO] [I
2
C] Other than the case of receiving data in the master operation mode, set FBYTE register of
the transmission FIFO to "8’h00".
⋅
[CSIO] When you configure the transmission data count for data reception in the master operation
mode, make sure that the transmission FIFO is empty and the SCR:TIE and SSR:TBIE bits are "0".
⋅
[CSIO] When you disable reception (SCR:RXE=0) while data is being received in the master operation
mode, you will need to disable the transmission FIFO before disabling the transmission/reception FIFO.
⋅
[CSIO] Make any change to reception FIFO’s FBYTE after disabled reception.
⋅
[LIN-UART] [I
2
C] Disable transmission and reception before making any change.
⋅
[I
2
C] When you configure the transmission data count for data reception in the master operation mode,
make sure that the transmission FIFO is empty and the SMR:TIE bit is "0".
⋅
[I
2
C] Before you disable the I
2
C interface (ISMK:EN=0) while data is being received in the master
operation mode, you will need to disable the transmission/reception FIFO first.
⋅
[I
2
C] When you configure the transmission data count for data reception in the master operation mode,
make sure that the transmission FIFO is empty and the SMR:TIE bit is "0".
⋅
[Common] Data configured at FBYTE of the reception FIFO should be "2" or greater.
⋅
[Common] You will not be able to use read-modify-write instructions for this register.
⋅
[Common] Settings that go over the FIFO capacity are prohibited.
MB91520 Series
MN705-00010-1v0-E
1341