Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
38
4.2.4.
Receive Data Register/Transmit Data Register:
RDR/TDR
RDR/TDR
The receive data register and transmit data register are located within the same addresses. When read, it
functions as the receive data register and when written, it functions as the transmit data register. When FIFO
is enabled, the address of RDR/TDR will be the address for reading/writing FIFO.
Read
RDR0n(n=0 to 11): Address Base addr + 06
H
(Access: Byte, Half-word, Word)
15
14
13
12
11
10
9
8
bit
-
D8
0
0
0
0
0
0
0
0
Initial value
R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX
R,W
Attribute
7
6
5
4
3
2
1
0
bit
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Initial value
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
Attribute
The receive data register (RDR) is a 9-bit data buffer register for serial data reception.
⋅
Serial data signals sent to the serial input pin (SIN pin) are converted in the shift register and stored in
the receive data register (RDR).
⋅
Depending on the data length, "0" is inserted in the upper bit as shown below.
Data length D8 D7 D6 D5 D4 D3 D2 D1 D0
9 bits
X
X
X
X
X
X
X
X
X
8 bits
0
X
X
X
X
X
X
X
X
7 bits
0
0
X
X
X
X
X
X
X
6 bits
0
0
0
X
X
X
X
X
X
5 bits
0
0
0
0
X
X
X
X
X
(X is the reception data bit)
⋅
When the received data is stored in the receive data register (RDR), the reception data full flag bit
(SSR:RDRF) will be set to "1". When reception interrupts are enabled (SSR:RIE=1), a reception
interrupt request will be generated.
⋅
The receive data register (RDR) should be read out when the reception data full flag bit (SSR:RDRF) is
"1". The reception data full flag bit (SSR:RDRF) will be automatically cleared to "0" when the receive
data register (RDR) has been read out.
⋅
In case a reception error occurs (SSR: PE, ORE or FRE is "1"), data in the receive data register (RDR)
will become invalid.
⋅
In operation mode 1 (multi-processor mode), the operation will be 7-bit or 8-bit long. The AD bit
received will be stored at the D8 bit.
⋅
For the 9-bit long transfer and in operation mode 1, RDR will be read in 16-bit access mode.
Notes:
⋅
When you use reception FIFO, if received data in the reception FIFO reaches specified number, "1" will
be set to RDRF.
⋅
When you are using reception FIFO, if the reception FIFO becomes empty, RDRF will be cleared to "0".
⋅
If a reception error occurs (SSR: PE, ORE, or FRE is "1") while using reception FIFO, the reception
FIFO enable bit will be cleared. As a result, data received will not be stored at the reception FIFO.
MB91520 Series
MN705-00010-1v0-E
1351