Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
39
Write
TDR0n(n=0 to 11): Address Base addr + 06
H
(Access: Byte, Half-word, Word)
15
14
13
12
11
10
9
8
bit
-
D8
-
-
-
-
-
-
-
1
Initial value
RX,WX RX,WX RX,WX RX,WX RX,WX RX,WX RX,WX RX,W
Attribute
7
6
5
4
3
2
1
0
bit
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
Initial value
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
Attribute
The transmit data register (TDR) is the 9-bit data buffer register for sending serial data.
⋅
When transmit operations are enabled (SCR:TXE=1), if transmission data is written to the transmit data
register (TDR), the transmission data is transferred to the transmit shift register and converted to serial
data, then output from the serial data output pin (SOT pin).
⋅
Depending on the data length, data will be invalidated from the upper bit as shown below.
Data length
D8
D7
D6
D5
D4 D3 D2 D1 D0
9 bits
X
X
X
X
X
X
X
X
X
8 bits
Invalid
X
X
X
X
X
X
X
X
7 bits
Invalid Invalid
X
X
X
X
X
X
X
6 bits
Invalid Invalid Invalid
X
X
X
X
X
X
5 bits
Invalid Invalid Invalid Invalid X
X
X
X
X
⋅
Transmission data empty flag (SSR:TDRE) will be cleared to "0" when the transmission data is written
to the transmit data register (TDR).
⋅
The transmission data empty flag (SSR:TDRE) will be set to "1" once a transmission starts after the
transmission data has been transferred to the transmit shift register if the transmission FIFO is disabled or
empty.
⋅
You will be able to write transmission data when the transmission data empty flag (SSR:TDRE) is set to
"1". If the transmission interrupt is enabled, a transmission interrupt will occur. Writing transmission data
should be performed by the generation of transmission interrupt or be done when the transmission data
empty flag (SSR:TDRE) is "1".
⋅
You will not be able to write transmission data when the transmission data empty flag (SSR:TDRE) is
"0" and transmission FIFO is disabled or full.
⋅
In operation mode 1 (multi-processor mode), the operation will be 7-bit or 8-bit long. The AD bit will be
transmitted by writing at the D8 bit.
⋅
For the 9-bit long transfer and in operation mode 1, write a value to the TDR in 16-bit access mode.
Notes:
⋅
Transmission data register is write-only register and receive data register is read-only register. The value
written is different from the read value since the transmission/reception registers are located at the same
address. Therefore instructions such as INC/DEC instructions which perform read-modify-write (RMW)
operation cannot be used.
⋅
For more information about the set timing of the transmission data empty flag (SSR:
TDRE) when using the transmission FIFO, see Section "36.7.2.4 Interrupts When Using Transmission
FIFO and Flag Setting Timing".
MB91520 Series
MN705-00010-1v0-E
1352