Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
44
4.2.7.
Serial timer Comparison Register: STMCR
Serial Timer Comparison Register (STMCR) sets the comparison value of a timer of the serial timer.
STMCRn(n=0 to 11) : Address Base addr + 0C
H
(Access: Byte, Half-word,
Word)
15
14
13
12
11
10
9
8
bit
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
7
6
5
4
3
2
1
0
bit
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
[bit15 to bit0] TC15-0: Comparison Bits
These bits set a comparison value for serial timer.
These bits will be compared with the Serial Timer Register (STMR) and when these bits and the values of
the STMR matched at the update timing of the STMR, the STMR will be set to "0". At this timing while
synchronous transmission is disabled (SACSR:TSYNE="0"), the timer interrupt flag (SACSR:INT) will be
set to "1" but when synchronous transmission is enabled (SACSR:TSYNE="1"), a transmission will be
started.
Notes:
⋅
When (0000)H is set to this register, the Serial Timer Register still indicates "0".
⋅
With "0000"H set to this register while synchronous transmission is disabled (SACSR:TSYNE="0"), the
timer interrupt flag (SACSR:TINT) will be fixed to “1” when the timer operating clock division value
(SACSR:TDIV) is set to "0000"b while the timer is running.
⋅
With synchronous transmission enabled (SACSR:TSYNE="1"), external trigger enabled
(SACSR:TRGE="1"), this register set with (0000)H, and when transmission data is present
(SSR:TDRE="0") while transmission is enabled(SCR:TXE="1"), the transmission will immediately be
started when any of external trigger edges set at the trigger selection bit (SACSR:TRG1, 0) is detected.
⋅
This register can be changed only when serial timer is disabled (SACSR:TMRE="0").
MB91520 Series
MN705-00010-1v0-E
1357