Fujitsu FR81S User Manual
FUJITSU SEMICONDUCTOR LIMITED
CONTENTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
CHAPTER 7: RESET .......................................................................................................................... 255
1.
O
VERVIEW
.................................................................................................................................. 256
2.
F
EATURES
................................................................................................................................... 257
3.
C
ONFIGURATION
.......................................................................................................................... 258
4.
R
EGISTERS
................................................................................................................................. 260
4.1.
Reset Source Register : RSTRR (ReSeT Result Register) ........................................... 261
4.2.
Reset Control Register : RSTCR (ReSeT Control Register) ......................................... 263
4.3.
CPU Abnormal Operation Register : CPUAR (CPU Abnormal operation Register) ...... 264
4.4.
PMU Status Register : PMUSTR (Power Management Unit STatus register) ............... 266
5.
O
PERATION
................................................................................................................................. 267
5.1.
Reset Level .................................................................................................................... 268
5.1.1.
Initialize Reset (INIT) ............................................................................................................................... 269
5.1.2.
Reset (RST) ............................................................................................................................................. 270
5.2.
Reset Factor .................................................................................................................. 271
5.2.1.
Power-on Reset ....................................................................................................................................... 272
5.2.2.
RSTX Pin Input ........................................................................................................................................ 273
5.2.3.
Watchdog Reset 0 ................................................................................................................................... 274
5.2.4.
Watchdog Reset 1 ................................................................................................................................... 275
5.2.5.
External Low-Voltage Detection Reset ................................................................................................. 276
5.2.6.
Illegal Standby Mode Transition Detection Reset ............................................................................... 277
5.2.7.
Internal Low-Voltage Detection Reset .................................................................................................. 278
5.2.8.
Flash Security Violation Reset ............................................................................................................... 279
5.2.9.
Software Reset (RSTCR:SRST)............................................................................................................ 280
5.2.10.
Recovery from Standby (Power Interception) ...................................................................................... 281
5.3.
Reset Acceptance .......................................................................................................... 282
5.3.1.
Generation of Reset Request ................................................................................................................ 283
5.3.2.
Acceptance of Reset Request ............................................................................................................... 284
5.3.3.
Reset Issue Delay Counter .................................................................................................................... 285
5.3.4.
Irregular Reset ......................................................................................................................................... 286
5.4.
Reset Issue .................................................................................................................... 287
5.4.1.
Super Initialize Reset (SINIT) ................................................................................................................ 288
5.4.2.
Initialize Reset (INIT) ............................................................................................................................... 290
5.4.3.
Reset (RST) ............................................................................................................................................. 291
5.5.
Reset Sequence ............................................................................................................ 292
5.5.1.
Reset Cycle .............................................................................................................................................. 293
5.5.2.
Reset Release.......................................................................................................................................... 294
5.5.3.
Operating Mode Fix ................................................................................................................................. 295
5.5.4.
Transition of Bus Control ........................................................................................................................ 296
5.5.5.
Reset Vector Fetch .................................................................................................................................. 297
5.5.6.
Reset and Forced Break ......................................................................................................................... 298
5.6.
Notes .............................................................................................................................. 299
CHAPTER 8: DMA CONTROLLER (DMAC)...................................................................................... 301
1.
O
VERVIEW
.................................................................................................................................. 302
2.
F
EATURES
................................................................................................................................... 303
3.
C
ONFIGURATION
.......................................................................................................................... 304
4.
R
EGISTERS
................................................................................................................................. 305
4.1.
DMA Control Register: DMACR (DMA Control Register) .............................................. 308
4.2.
DMA Channel Control Register 0 to 15: DCCR0 to 15 (DMA Channel Control Register 0 to
15) ................................................................................................................................ 310
4.3.
DMA Channel Status Register 0 to 15 : DCSR0 to 15: (DMA Channel Status Register 0 to
15) ................................................................................................................................ 316
4.4.
DMA Transfer Count Register 0 to 15 : DTCR0 to 15: (DMA Transfer Count Register 0 to
15) ................................................................................................................................ 318
4.5.
DMA Transfer Source Register 0 to 15 : DSAR0 to 15: (DMA Source Address Register 0
to 15) ............................................................................................................................ 319
4.6.
DMA Transfer Destination Register 0 to 15 : DDAR0 to 15 (DMA Destination Address
Register 0 to 15) ........................................................................................................... 320
MB91520 Series
MN705-00010-1v0-E
(12)