Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

4. Registers

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

Bit name

Function

bit5 SPI:

SPI support bit

This bit is used to execute a SPI communication.

When chip select is used in master mode (SCR: MS=0), this bit is used for

serial chip select pin 0 communication.

When this bit is set to "0": Normal synchronous communication

When this bit is set to "1": SPI communication supported.

Notes:

⋅

Set this bit when transmission and reception are disabled

(TXE=RXE=0).

⋅

This bit is used in one of cases below.

⋅

Chip select pin is disabled (SCSCR:CSEN3-0="0000"b)

⋅

When mode is in slave (SCR:MS=1)

⋅

When data format of chip select is disabled (ESCR:CSFE=0)

⋅

When data format of chip select is enabled (ESCR:CSFE=1) and serial

chip select pin 0 is active

bit4 RIE:

Reception interrupt enable

bit

⋅

This bit enables or disables the output of reception interrupt request to

the CPU.

⋅

When the RIE bit and reception data flag bit (SSR:RDRF) are set to "1",

or any of the error flag bit (ORE) is set to "1", a reception interrupt

request will be output.

bit3 TIE:

Transmission interrupt

enable bit

⋅

This bit enables or disables the output of transmission interrupt request to

the CPU.

⋅

When the TIE bit and the SSR:TDRE bit are set to "1", a transmission

interrupt request will be output.

bit2 TBIE:

Transmission bus idle

interrupt enable bit

⋅

This bit enables or disables the output of transmission bus idle interrupt

request to the CPU.

⋅

When the TBIE bit and SSR:TBI bit are set to "1", a transmission bus

idle interrupt request will be output.

bit1 RXE:

Reception enable bit

This bit enables/disables the reception of CSIO.

⋅

If this bit is set to "0", data frame reception is disabled.

⋅

If this bit is set to "1", data frame reception is enabled.

Notes:

⋅

If you disable reception (RXE=0) while a reception is in progress, it

immediately stops the reception.

⋅

After MS and SMR:SCINV bits are set, set reception enable (RXE=1).

bit0 TXE:

Transmission enable bit

This bit enables/disables the transmission of CSIO.

⋅

If this bit is set to "0", data frame transmission is disabled.

⋅

If this bit is set to "1", data frame transmission is enabled.

Note:

If you disable transmission (TXE=0) while a transmission is in progress,

it immediately stops the transmission.

MB91520 Series

MN705-00010-1v0-E

1362