Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
55
Example: When you read "AAAA5555"h with 32 bits data length:
Number of read
from RDR
D31 D16
D15 D0
First
"0000"
H
"5555"
H
Second
"0000"
H
"AAAA"
H
When you select one of upper bits (SSR:ES=1), first read must be upper 16 bits of received data and second
read must be lower 16 bits of received data.
Example: When you read "AAAA5555"h with 32 bits data length:
Number of read
from RDR
D31 D16
D15 D0
First
"0000"
H
"AAAA"
H
Second
"0000"
H
"5555"
H
Notes:
⋅
When you use reception FIFO, if received data in the reception FIFO reaches specified number, "1" will
be set to RDRF.
⋅
When you are using reception FIFO, if the reception FIFO becomes empty, RDRF will be cleared to "0".
⋅
If a reception error occurs (SSR: ORE is "1") while using reception FIFO, the reception FIFO enable bit
will be cleared. As a result, data received will not be stored at the reception FIFO.
MB91520 Series
MN705-00010-1v0-E
1368