Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
58
4.3.5.
Serial Aid Control Status Register: SACSR
The serial aid control status register (SACSR) allows you to control serial test operations, select how to
activate the serial timer, enable/disable timer interrupts, enable/disable synchronous transmission, set the
division value of the operating clock of the serial timer, and enable/disable the serial timer.
SACSRn(n=0 to 11) : Address Base addr + 08
H
(Access: Byte, Half-word,
Word)
15
14
13
12
11
10
9
8
bit
STST Reserved TBEEN CSEIE
CSE
TRG1
TRG0
TINT
0
0
0
0
0
0
0
0
Initial value
R/W
R0,W0
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
7
6
5
4
3
2
1
0
bit
TINTE TSYNE TRGE TDIV3 TDIV2 TDIV1 TDIV0 TMRE
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
[bit15] STST: Serial test bit
This bit is used to enable or disable the serial test mode.
When the serial test mode is enabled, SOUT and SIN will be connected inside the multi-function serial
interface, and data to be transmitted from SOUT can be received from SIN without being processed.
When the serial test mode is enabled, the SOUT pin will be fixed to "H", and data input into the SIN pin
will be ignored.
STST
Serial test bit
0
Serial test mode disabled
1
Serial test mode enabled
[bit14] Reserved
Read: The read value is "0".
Write: Always write "0" to this bit.
[bit13] TBEEN: Transfer byte error enable bit
If one of the following conditions applies in the master mode (SCR:MS="0") and if no valid transmission
data is available (SSR:TDRE="1") for the transmission data register (TDR) when one frame has been
transmitted while the number of frames that are being transmitted is smaller than the setting value of
TBYTE, this bit is used to enable/disable occurrence of serial chip select errors.
⋅
Chip select is used
⋅
Synchronous transmission of the serial timer is used
⋅
Transmission activated by an external trigger is used
TBEEN
Transfer byte error enable bit
0
Occurrence of chip select errors in the master mode (SCR:MS=0)
disabled
1
Occurrence of chip select errors in the master mode (SCR:MS=0)
enabled
Note:
This bit can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
MB91520 Series
MN705-00010-1v0-E
1371