Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
65
Notes:
⋅
These bits can be changed only when transmission and reception are disabled (SCR:TXE=RXE="0").
⋅
If the same value is set to both the serial chip select start bits (SST1, SST0) and the serial chip select end
bits (SED1, SED0), only the serial chip select pin set by these bits will become active.
⋅
In the slave mode (SCR:MS="1"), setting these bits has no effect.
⋅
Only the serial chip select pin with serial chip select enabled (CSEN="1") will become active.
[bit11, bit10] SCD1-0: Serial chip select display bits
These bits are used to display a pin where serial chip select is active.
SCD1
SCD0
Display pin
0
0
SCS0
0
1
SCS1
1
0
SCS2
1
1
SCS3
Notes:
⋅
If a serial chip select pin is inactive, the serial chip select pin which becomes active next time will be
displayed.
⋅
These bits will be set to "00b" when the slave mode is selected (SCR:MS="1"), software reset is
triggered (SCR:UPCL="1"), or transmission is disabled (SCR:TXE="0").
[bit9] SCAM: Serial chip select active retain bit
This bit is used to select whether to retain the active state of a serial chip select pin or not. When this bit is
set to "1", the serial chip select pin will not become inactive, even if transmission operation has completed
(SSR:TBI="1") after a serial chip select pin becomes active. If this bit is set to "0" when a serial chip select
pin is active and this bit is set to "1", the serial chip select pin will become inactive after transmission has
completed.
SCAM
Serial chip select active retain bit
0
Inactive state of a serial chip select pin not retained
1
Active state of a serial chip select pin retained
Notes:
⋅
If transmission is disabled (SCR:TXE="0") and software reset is triggered (SCR:UPCL="1"), a serial
chip select pin will become inactive regardless of the value of this bit.
⋅
When a serial chip error occurs (SACSR:CSE=1), a serial chip select pin will become inactive regardless
of the value of this bit.
[bit8 to bit6] CDIV2-0: Serial chip select timing operating clock division bits
These bits are used to set the division ratio of a serial chip select timing operating clock.
CDIV2 CDIV1 CDIV0
Serial chip select timing operating clock
Division
ratio
φ
=
8MHz
φ
=
10MHz
φ
=
16MHz
φ
=
20MHz
φ
=
24MHz
φ
=
32MHz
0
0
0
φ
125ns
100ns
62.5ns
50ns
41.67ns 31.25ns
0
0
1
φ
/2
250ns
200ns
125ns
100ns 83.33ns 62.5ns
0
1
0
φ
/4
500ns
400ns
250ns
200ns 166.67ns 125ns
0
1
1
φ
/8
1µs
800ns
500ns
400ns 333.33ns 250ns
1
0
0
φ
/16
2µs
1.6µs
1µs
800ns 666.67ns 500ns
1
0
1
φ
/32
4µs
3.2µs
2µs
1.6µs
1.33µs
1µs
1
1
0
φ
/64
8µs
6.4µs
4µs
3.2µs
2.67µs
2µs
φ
: Bus clock
MB91520 Series
MN705-00010-1v0-E
1378